Ting-En Hsieh

Gate Recessed Quasi-Normally OFF Al 2 O 3 /AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer

In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of ~109.

GaN MIS-HEMTs With Nitrogen Passivation for Power Device Applications

A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.

Effect of high voltage stress on the DC performance of the Al2O3/AlN GaN metal–insulator–semiconductor high-electron mobility transistor for power applications

We demonstrate an Al2O3/AlN/AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistor (MIS-HEMT) device with stable electrical properties under high-voltage stress, by using an Al2O3/AlN stack layer as the gate dielectric layer. Excellent quality AlN/Al2O3 GaN interface was obtained by using plasma-enhanced ALD (PE-ALD), resulting in a very low interface trap density (Dit) of ~1.8 × 1011 eV−1 cm−2, obtained by using the conductance method. The device exhibits a small threshold voltage hysteresis of ~200 mV and a lower gate–source leakage current. No obvious changes in the drain–source current and ON-resistance were observed for the device that was subject to the drain–source voltage stress of 100 V for 15 h.

Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect

We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.

Bias- and temperature-assisted trapping/de-trapping of ron degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate

In this study, we investigate the Ron degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase Ron degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the Ron degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases further, the Ron degradation is reduced. Third, the Ron degradation slowly increases again. Ron degradation is characterized with different temperatures, the results show that 1) high temperature leads to a smaller Ron degradation compared to the result at room temperature and 2) high temperature shifts the peak of the Ron degradation at a lower drain bias. A possible mechanism that the trapping and de-trapping could occur due to the high temperature and high drain bias is proposed to explain the observed results.

The effect of surface passivation on the electrical performance of Al-GaN/GaN HEMTs with slant field plates

Summary form only given. We have investigated the effects of surface passivation thickness on the electrical performance of Al-GaN/GaN HEMTs with slant field plates. It is found that the existence of the silicon nitride passivation layer helps to improve the DC characteristics of the devices in terms of the lower drain current collapse, higher maximum DC transconductance, and higher maximum drain current. RF wise, the devices with passivation suffer from lower fT and fMAX due to the increase in the gate capacitances. However, an improvement of RF output power was observed for devices with passivation layer thickness up to 300 nm.