Tingkai Li

Resistance random access memory switching mechanism

The properties of Pr0.7Ca0.3MnO3 resistance random access memory devices have been studied in terms of electrical pulse width, pulse polarity, film thickness, resistivity distribution, temperature dependence, device impedance, and dynamics property. Based on the experimental data it is concluded that the resistance increase is due to localization of valence electrons. Voltage pulse induced high density of excessive nonequilibrium electrons near the cathode of the device caused the free valence electrons in transition metal oxide to be localized, the well known Jahn-Teller effect. The voltage pulse induced reduction of resistance is due to delocalization of localized valence electrons by high electric fields.The properties of Pr0.7Ca0.3MnO3 resistance random access memory devices have been studied in terms of electrical pulse width, pulse polarity, film thickness, resistivity distribution, temperature dependence, device impedance, and dynamics property. Based on the experimental data it is concluded that the resistance increase is due to localization of valence electrons. Voltage pulse induced high density of excessive nonequilibrium electrons near the cathode of the device caused the free valence electrons in transition metal oxide to be localized, the well known Jahn-Teller effect. The voltage pulse induced reduction of resistance is due to delocalization of localized valence electrons by high electric fields.

Growth of GaN film on 150mm Si (111) using multilayer AlN∕AlGaN buffer by metal-organic vapor phase epitaxy method

High quality GaN film was successfully grown on 150mm Si (111) substrate by metal-organic vapor phase epitaxy method using AlN multilayer combined with graded AlGaN layer as buffer. The buffer layer structure, film quality, and film thickness are critical for the growth of the crack-free GaN film on Si (111) substrate. Using multilayer AlN films grown at different temperatures combined with graded Al1−xGaxN film as the buffer, the tensile stress on the buffer layer was reduced and the compressive stress on the GaN film was increased. As a result, high quality 0.5μm crack-free GaN epitaxial layer was successfully grown on 6in. Si substrate.

Fabrication and characterization of a Pb5Ge3O11 one-transistor-memory device

A Pb5Ge3O11 metal–ferroelectric–metal–oxide–silicon memory transistor has been fabricated. The device showed a memory window of about 2 V. The memory window was almost saturated at the operation voltage of 2 V. The “off” state drain current (ID) at VD of 0.1 V and VG of 0.5 V is about 1×10−8 A. The “on” state drain current (ID) at VD of 0.1 V and VG of 0.5 V is about 1×10−6 A, which is 100 times high than that of off state.

The ferroelectric properties of c-axis oriented Pb5Ge3O11 thin films prepared by metalorganic chemical vapor deposition

C-axis oriented ferroelectric Pb5Ge3O11 thin films were prepared on Pt/Ir-coated Si wafers by metalorganic chemical vapor deposition (MOCVD) and rapid thermal process annealing techniques. The films were specular and crack free and showed complete crystallization with c-axis orientation for growth temperatures between 500 and 550 °C. Good ferroelectric properties were obtained for a 150-nm-thick film with Pt/Ir electrodes: the remanent polarization (2Pr) and coercive field (2Ec) values were about 3.8 μC/cm2 and 93 kV/cm, respectively. The films also showed excellent fatigue characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage current increased with increasing applied voltage, and is about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant showed behavior similar to most ferroelectric materials in that the dielectric constant changed with applied voltages. The maximum dielectric constant is about 45. High-quality MOCVD Pb5Ge3O11 films can be used for single transistor ferroe...

Semiconductive metal oxide ferroelectric memory transistor: A long-retention nonvolatile memory transistor

The retention problem is a technical challenge for one-transistor (1T) ferroelectric memory devices. Three possible mechanisms are responsible for the poor retention of one-transistor ferroelectric memories: namely, charges trapping within the gate oxide and ferroelectric film, floating gate effect, and the depolarization field. In order to overcome these problems, a novel ferroelectric transistor design using a semiconductive oxide film in place of the gate dielectric has been fabricated. There is no insulator, other than the ferroelectric thin film in the gate stack; therefore, there is a very low depolarization field. The bottom gate of the ferroelectric capacitor is electrically connected to the silicon substrate through the semiconductive metal oxide resulting in the improvement of the memory retention characteristics.

Effects of AlxGa1−xN interlayer for GaN epilayer grown on Si substrate by metal-organic chemical-vapor deposition

GaN film grown on Si substrate using multilayer AlN/AlxGa1−xN buffer is studied by the low-pressure metal-organic chemical-vapor deposition method. The AlxGa1−xN films with Al composition varying from 1 to 0.66 were used to accommodate the stress induced between GaN and the Si substrate during GaN growth. The correlation of the Al composition in the AlxGa1−xN films with respect to the stress induced in the GaN film grown was studied using high-resolution x-ray diffraction, including symmetrical and asymmetrical ω/2θ scans and reciprocal space maps. It is found that with proper design of the Al composition in the AlxGa1−xN buffer layer, crack-free GaN film can be successfully grown on 6 in. Si (111) substrates using multilayer AlN and AlxGa1−xN buffer layers.

Photoluminescence and Electroluminescence Studies on Tb-Doped Silicon Rich Oxide Materials and Devices

Photoluminescence (PL) characteristics of Tb-doped silicon rich oxide (SRO) films prepared by DC-sputtering and post-annealing processes were studied. The silicon richness of the SRO film could be controlled by varying the sputtering power and oxygen concentration in the sputtering chamber. PL emission from the as-deposited sample was found to be composed of Tb3+ intra 4f transition-related emission and the silicon nano particle-related broad bandwidth emission. Thermal annealing could significantly improve the material properties as well as the PL signals. PL properties depended strongly upon the annealing scheme and silicon richness. Annealing at high temperatures (900 ∼ 1050 °C) enhanced Tb-related emission and suppressed the silicon nano particle-related emission. For samples with different silicon richness, annealing at 950 °C was found to produce higher PL signals than at other temperatures. It was attributed more to lifetime quenching than to concentration quenching. Electroluminescent (EL) devices with a capacitor structure were fabricated, the optimized process condition for the EL device was found to be different from that of PL emission. Among the annealing schemes that were used, wet oxidation was found to improve device performance the most, whereas, dry oxidation was found to improve material property the most. Wet oxidation allowed the breakdown electrical field to increase significantly and to reach above 10 mV·cm−1. The EL spectra showed a typical Tb3+ emission, agreeing well with the PL spectra. The I-V measurements indicated that for 100 nm thick film, the Fowler-Nordheim tunneling started at an electrical field of around 6 mV·cm−1 and the light emission became detectable at a current density of around 10−4 A ·cm−2 and higher. Strong electroluminescence light emission was detected when the electrical field was close to 10 mV·cm−1.

Comparison of MFMOS and MFOS One Transistor Memory Devices

Pt/PGO/HfO 2 /Si (MFOS) and Pt/PGO/Ir/Polysilicon/SiO 2 /Si (MFOS) and Pt/PGO/Ir/Polysilicon/SiO 2 /Si (MFMPOS) one-transistor devices have also been fabricated. The working functions and properties of both Pt/PGO/HfO 2 /Si (MFMPOS) one-transistor devices have also been measured. Compared with PGO MFOS one-transistor devices, PGO MFMPOS one-transistor devices showed lower operation voltage, smaller sub-threshold voltage swing, larger memory windows and better retention properties, but more difficult integration processes. In order to find the reasons for the different properties between MFOS and MFMPOS one-transistor devices, the relationship between the properties and structures, including interface and microstructure, has been investigated and discussed.

INTEGRATION PROCESSES AND PROPERTIES OF SEMICONDUCTIVE OXIDE MEMORY TRANSISTOR

ABSTRACT The retention problem is a technical challenge for one-transistor (1T) ferroelectric memory devices. Three possible mechanisms are responsible for the poor retention of one-transistor ferroelectric memories: namely, leakage current deals with charges trapping within the gate oxide and ferroelectric film, floating gate effect, and the depolarization field. In order to overcome these problems, a novel ferroelectric transistor design using a semiconductive oxide film in place of the gate dielectric has been fabricated. There is no insulator and floating gate, and only the ferroelectric thin film deposited on a semiconductive oxide in the gate stack; therefore, there is a very low depolarization field. The highly oriented ferroelectric thin films have been selectively deposited on the device trench structure, which resulted in lower leakage current. The bottom gate of the ferroelectric capacitor is electrically connected to the silicon substrate through the semiconductive metal oxide resulting in the improvement of the memory retention characteristics.

The Effects of Integration Processes on Properties of One Transistor MFMPOS Memory Devices

Integration processing of one-transistor memory devices deals with the following issues: film quality of ferroelectric materials, integration process induced damages such as etching and forming gas annealing damage of ferroelectric materials, the alignment for devices. In order to make high quality one-transistor memory devices, integration processes including nitride gate replacement, oxide trench etching structures, selective deposition, etc. have been investigated for fabrication of one transistor MFMPOS (M: Metal, F: Ferroelectrics, M: Metal, P: polysilicon, O: oxide, S: silicon) memory devices. The integration processes for one transistor memory device have also been optimized to reduce process-induced damages. Based on the experimental results, MOCVD selective deposition can make higher quality patterned ferroelectric thin films, damascene structure with CMP processes can reduce the etching damages. Therefore, the high quality one transistor MFMPOS memory devices have been made.