Tingyu Bai

Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding

The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure ( 20 MPa. The combined reduction of dielet interconnect pitch, dielet-to-dielet spacing and trace pitch will enable a Moores law for packaging.

Direct visualization of thermal conductivity suppression due to enhanced phonon scattering near individual grain boundaries

Understanding the impact of lattice imperfections on nanoscale thermal transport is crucial for diverse applications ranging from thermal management to energy conversion. Grain boundaries (GBs) are ubiquitous defects in polycrystalline materials, which scatter phonons and reduce thermal conductivity (κ). Historically, their impact on heat conduction has been studied indirectly through spatially averaged measurements, that provide little information about phonon transport near a single GB. Here, using spatially resolved time-domain thermoreflectance (TDTR) measurements in combination with electron backscatter diffraction (EBSD), we make localized measurements of κ within few μm of individual GBs in boron-doped polycrystalline diamond. We observe strongly suppressed thermal transport near GBs, a reduction in κ from ∼1000 W m-1 K-1 at the center of large grains to ∼400 W m-1 K-1 in the immediate vicinity of GBs. Furthermore, we show that this reduction in κ is measured up to ∼10 μm away from a GB. A theoretical model is proposed that captures the local reduction in phonon mean-free-paths due to strongly diffuse phonon scattering at the disordered grain boundaries. Our results provide a new framework for understanding phonon-defect interactions in nanomaterials, with implications for the use of high-κ polycrystalline materials as heat sinks in electronics thermal management.

Probing Growth-Induced Anisotropic Thermal Transport in High-Quality CVD Diamond Membranes by Multifrequency and Multiple-Spot-Size Time-Domain Thermoreflectance

The maximum output power of GaN-based high-electron mobility transistors is limited by high channel temperature induced by localized self-heating, which degrades device performance and reliability. Chemical vapor deposition (CVD) diamond is an attractive candidate to aid in the extraction of this heat and in minimizing the peak operating temperatures of high-power electronics. Owing to its inhomogeneous structure, the thermal conductivity of CVD diamond varies along the growth direction and can differ between the in-plane and out-of-plane directions, resulting in a complex three-dimensional (3D) distribution. Depending on the thickness of the diamond and size of the electronic device, this 3D distribution may impact the effectiveness of CVD diamond in device thermal management. In this work, time-domain thermoreflectance is used to measure the anisotropic thermal conductivity of an 11.8 μm-thick high-quality CVD diamond membrane from its nucleation side. Starting with a spot-size diameter larger than the thickness of the membrane, measurements are made at various modulation frequencies from 1.2 to 11.6 MHz to tune the heat penetration depth and sample the variation in thermal conductivity. We then analyze the data by creating a model with the membrane divided into ten sublayers and assume isotropic thermal conductivity in each sublayer. From this, we observe a two-dimensional gradient of the depth-dependent thermal conductivity for this membrane. The local thermal conductivity goes beyond 1000 W/(m K) when the distance from the nucleation interface only reaches 3 μm. Additionally, by measuring the same region with a smaller spot size at multiple frequencies, the in-plane and cross-plane thermal conductivities are extracted. Through this use of multiple spot sizes and modulation frequencies, the 3D anisotropic thermal conductivity of CVD diamond membrane is experimentally obtained by fitting the experimental data to a thermal model. This work provides an improved understanding of thermal conductivity inhomogeneity in high-quality CVD polycrystalline diamond that is important for applications in the thermal management of high-power electronics.

Characterization of interfacial morphology of low temperature, low pressure Au–Au thermocompression bonding

M.S. Goorsky1,4, K. Schjølberg-Henriksen2, B. Beekley1, T. Bai1, K. Mani1, P. Ambhore1,4, A. Bajwa1,4, N. Malik3 and S.S. Iyer,1,4 1Materials Science and Engineering, University of California, Los Angeles. 90095, USA 2SINTEF ICT, P.O. Box 314 Blindern, 0314 Oslo, Norway 3Centre for Materials Science and Nanotechnology, University of Oslo, 0316 Oslo, Norway 4Center for Heterogeneous Integration and Performance Scaling, University of California, Los Angeles. 90095, USA

Low Thermal Boundary Resistance Interfaces for GaN-on-Diamond Devices

The development of GaN-on-diamond devices holds much promise for the creation of high-power density electronics. Inherent to the growth of these devices, a dielectric layer is placed between the GaN and diamond, which can contribute significantly to the overall thermal resistance of the structure. In this work, we explore the role of different interfaces in contributing to the thermal resistance of the interface of GaN/diamond layers, specifically using 5 nm layers of AlN, SiN, or no interlayer at all. Using time-domain thermoreflectance along with electron energy loss spectroscopy, we were able to determine that a SiN interfacial layer provided the lowest thermal boundary resistance (<10 m2K/GW) because of the formation of an Si-C-N layer at the interface. The AlN and no interlayer samples were observed to have TBRs greater than 20 m2K/GW as a result of a harsh growth environment that roughened the interface (enhancing phonon scattering) when the GaN was not properly protected.

The stability of metallized, thin, flexible III–V structures for high temperature applications and wafer bonding

The stability of thin, flexible III-V layers / solar cells with metallization was addressed. Reduced cell thickness (reduced weight) places added constraints on metallization sequences, thicknesses, and thermal budgets for these cells. We subjected a structure of a thin (few μm) III-V layers (the focus here is on InP-based structures) with metallization backing (Au, Ni, and Cu-based metallizations, several μm thick) to annealing at 200 °C, 300 °C, or 400 °C for up to a twelve hours. X-ray diffraction is a particularly useful technique as measurements from the solar cell (semiconductor) side of the stack also reveals the metallization diffraction peaks and hence any reaction byproducts. This is due to the beam penetration through the few μm thick cell layers. After 200 °C for twelve hours, x-ray diffraction and transmission electron microscopy indicate reactions between the metal layers in the stack but the semiconductor is unchanged. After 300 °C, twelve hours, there is more extensive intermetallic compound formation. However, after annealing at 400 °C, twelve hours, the III-V layer is entirely consumed. In contrast, when much thicker cells / semiconductor layers are subject to similar annealing conditions, there may not be a significant impact on performance because only a few μm of the total cell thickness is consumed. When the total thickness is only a few μm, however, the reaction between the metal contact layer and the semiconductor leads to consumption of the entire device. These results demonstrate that (i) the total cell thickness is important when considering contact-semiconductor interactions at elevated operating or processing temperatures and (ii) x-ray diffraction through the thin cell provides a detailed assessment of reactions; it can be utilized for any combination of thin film solar cell and metallization.