Tinus Stander

A comparison of basic 94 GHz planar transmission line resonators in commercial BiCMOS back-end-of-line processes

A comparative simulation study of planar 94 GHz resonators in a typical BiCMOS BEOL stack-up is presented, with the effect of chip passivation included. It is shown that Q-factors of between 3 and 15 can be obtained, depending on transmission medium and ground plane layer choice. Straight half-wavelength and shorted quarter-wavelength microstrip resonators are shown to outperform CPW, GCPW and hairpin resonators, with highest Q-factors obtained where the lowest available metallization layer is used as ground plane. Q-factors of above 10 may also be achieve in the absence of any ground plane in CPW, which may be implemented in processes (such as GaAs or GaN) where multiple metallization layers are not readily available.

A review of key development areas in low-cost packaging and integration of future E-band mm-wave transceivers

With an ever increasing number of broadband applications in sub-Saharan Africa, mm-wave point-to-point networking has the potential to fill a niche in communications network architectures. Widespread adoption of this technology would benefit from conventional RF soft substrate integration and packaging, as opposed to system-on-chip or thick film processes. A review on the state-of-the-art in E-band soft substrate systems reveals significant reliance on MMICs. We propose that hybrid integration of active devices with off-chip passives, as well as better integration of active components in SIW, will lead to better performing E-band systems in soft substrates. Specific enabling techniques from the microwave domain are identified.

Development, simulation and construction of cost-effective GTEM cells

Gigahertz transverse electromagnetic (GTEM) cells are used extensively in industry for testing the impact of defined E-fields on devices sensitive to electromagnetic interference. Compared to anechoic chambers, GTEM cells are small, inexpensive and require less powerful amplifiers to achieve the same field strength. This paper presents the design, simulation and qualification of a compact GTEM cell capable of generating field strengths in excess of 600 V/m over a 20 × 20 × 15 cm test cavity, whilst being less than 2.2 × 1.3 × 1 m in total size. Specific hybrid FEM-MLFMM simulation strategies are provided to examine high power device characteristics prior to manufacturing, including accurate modelling of absorber materials. Practical notes on manufacturing and qualification are also presented.

A comparison of simple low-power wedge-type X-band waveguide absorbing load implementations

Two inexpensive waveguide absorbing loads are constructed and measured, each using a single thin resistive sheet absorber supported by styrofoam walls, and 50 mm in length. It is found that a V-cut wedge displays less reflection than a tapered wedge, with -30 dB reflection across a band 8.5 - 12.4 GHz.

Oscillation-Based Test Applied to a Wideband CCII

The Argentina-South Africa Research Cooperation Programme, as administered by the Ministry of Science, Technology and Productive Innovation in Argentina and the National Research Foundation in South Africa.

An L-band tapered-ridge SIW-to-CPW transition

A tapered ridge transition between coplanar waveguide and substrate-integrated waveguide is presented. The taper is implemented through staircase metallization across 10 layers of conventional RF substrate with sidewall expansion and upper cut-out using Vivaldi-type exponential tapers. Fractional bandwidth of 36% is achieved in the L-band, with insertion loss of 0.5 dB and return loss of 15 dB.

An on-chip post-production tunable group delay equaliser

A design method for distributed element on-chip post-production tunable group delay equalising networks is presented. It is shown that a number of adjustable Darlington C-sections can be used to equalise the group delay of an arbitrary network. The C-sections are implemented in an IBM 0.13 μm BiCMOS process as complementary microstrip slotline-stub all-pass structures and modified to provide post-production tunability. The group delay ripple of a theoretical second-order Butterworth bandpass filter, cascaded with the synthesised all-pass network, is reduced by 43% as proof of concept.

Ultra-compact capacitively loaded evanescent half-mode SIW filters for LTE applications

Abstract This paper presents a novel miniaturized substrate integrated waveguide filter by combining both half-mode resonators and capacitive loading on a conventional two-layer printed circuit board (PCB) process. The resulting synthesis is successfully demonstrated in an long-term evolution application by means of a third-order filter of< 225 mm2 in size while featuring 2.3 dB insertion loss over a 5.5% fractional bandwidth at 3.7 GHz. Good first-iteration agreement between simulated and measured results, both in center frequency ...

Broadband effect of linear tapered transitions between probe pads and GCPW signal lines on-chip

To effect a low-reflection interconnect between GSG probe pads and on-chip GCPW, a linear taper between the signal pad and the GCPW signal line is often included. This work evaluates, both in parametric simulation and experimentation, the effect of this taper shape to the input reflection in the band 1 – 110 GHz. It is found that, although longer tapers offer some advantage below 30 GHz, the taper ultimately impedes the input reflection of the interconnect.

Oscillation-based test in a CCII-based bandpass filter

Oscillation based testing (OBT) has proven to be a simple yet effective VLSI test for numerous circuit types. In this work, OBT is applied to test Second-generation Current Conveyor (CCII) based filters for the first time. Adopting a CCII-based band pass filter as a case study, it is shown that OBT can be implemented with a minimally intrusive switched feedback loop to establish the oscillator. Exhaustive fault simulation indicates 98.11% detection of possible short circuit and 100% detection of possible open circuit faults in the circuit under test, in both 0.35μm and 1.2μm CMOS technology nodes.