Tobias Delbrück

White noise in MOS transistors and resistors

The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations.<<ETX>>

Silicon retina with correlation-based, velocity-tuned pixels

A functional two-dimensional silicon retina that computes a complete set of local direction-selective outputs is reported. The chip motion computation uses unidirectional delay lines as tuned filters for moving edges. Photoreceptors detect local changes in image intensity, and the outputs from these photoreceptors are coupled into the delay line, where they propagate with a particular speed in one direction. If the velocity of the moving edges matches that of the delay line, then the signal on the delay line is reinforced. The output of each pixel is the power in the delay line signal, computed within each pixel. This power computation provides the essential nonlinearity for velocity selectivity. The delay line architecture differs from the usual pairwise correlation models in that motion information is aggregated over an extended spatiotemporal range. As a result, the detectors are sensitive to motion over a wide range of spatial frequencies. The design of functional one- and two-dimensional silicon retinas with direction-selective, velocity-tuned pixels is described. It is shown that pixels with three hexagonal directions of motion selectivity are approximately (225 mu m)/sup 2/ in area in a 2- mu m CMOS technology and consume less than 5 mu W of power. >A functional two-dimensional silicon retina that computes a complete set of local direction-selective outputs is reported. The chip motion computation uses unidirectional delay lines as tuned filters for moving edges. Photoreceptors detect local changes in image intensity, and the outputs from these photoreceptors are coupled into the delay line, where they propagate with a particular speed in one direction. If the velocity of the moving edges matches that of the delay line, then the signal on the delay line is reinforced. The output of each pixel is the power in the delay line signal, computed within each pixel. This power computation provides the essential nonlinearity for velocity selectivity. The delay line architecture differs from the usual pairwise correlation models in that motion information is aggregated over an extended spatiotemporal range. As a result, the detectors are sensitive to motion over a wide range of spatial frequencies. The design of functional one- and two-dimensional silicon retinas with direction-selective, velocity-tuned pixels is described. It is shown that pixels with three hexagonal directions of motion selectivity are approximately (225 mum)(2) in area in a 2-mum CMOS technology and consume less than 5 muW of power.

Orientation-selective aVLSI spiking neurons

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity

The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons

Scanners for visualizing activity of analog VLSI circuitry

This paper tutorially describes mixed digital-analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple one-dimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers. We discuss practical details of design and performance, and we give a source for example scanner layout.

Linear Systems Theory

This chapter contains sections titled: Linear Shift-Invariant Systems, Convolution, Impulses, Impulse Response of a System, Resistor-Capacitor Circuits, Higher Order Equations, The Heaviside-Laplace Transform, Linear Systems Transfer function, The Resistor-Capacitor Circuit (A Second Look), Low-Pass, High-Pass, and Band-Pass Filters

A Spike-Based Saccadic Recognition System

The paper presents a spike-based saccadic recognition system that uses a temporal-derivative silicon retina on a pan-tilt unit and an aVLSI multi-neuron classifier with a time-to-first-spike output coding. By using the spike information during the last 150 ms of a saccadic movement, we generate a reliable, sparse stimulus representation of image patches. The paper describes a novel classification scheme where the retinal spikes during this time influence the time-to-first spike of classifier neurons which receive the same constant input current. The preferred pattern of the neuron is stored in the synaptic connectivity between the retina and the classifier neuron. The authors demonstrates the robustness and real-time performance of this recognition scheme on a saccadic system which uses analog VLSI components.

Modeling orientation selectivity using a neuromorphic multi-chip system

The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel, distributed networks of integrate-and-fire (I&F) neurons. We have developed a reconfigurable multi-chip neuronal system for modeling feature selectivity and applied it to oriented visual stimuli. Our system comprises a temporally differentiating imager and a VLSI competitive network of neurons which use an asynchronous address event representation (AER) for communication. Here we describe the overall system, and present experimental data demonstrating the effect of recurrent connectivity on the pulse-based orientation selectivity

Retinal ganglion cell software and FPGA model implementation for object detection and tracking

This paper describes the software and FPGA implementation of a Retinal Ganglion Cell model which detects moving objects. It is shown how this processing, in conjunction with a Dynamic Vision Sensor as its input, can be used to extrapolate information about object position. Software-wise, a system based on an array of these of RGCs has been developed in order to obtain up to two trackers. These can track objects in a scene, from a still observer, and get inhibited when saccadic camera motion happens. The entire processing takes on average 1000 ns/event. A simplified version of this mechanism, with a mean latency of 330 ns/event, at 50 MHz, has also been implemented in a Spartan6 FPGA.

22.5 A 0.5V 55µW 64×2-channel binaural silicon cochlea for event-driven stereo-audio sensing

Event-driven DSPs have the advantage of activity-dependent power consumption [1], and event-driven neural networks have shown superior power efficiency in real-time recognition tasks [2]. A bio-inspired silicon cochlea [3] functionally transforms sound input into multi-frequency-channel asynchronous event output, and hence is the natural candidate for the audio sensing frontend of event-driven signal processing systems like [1] and [2]. High-quality event encoding can be implemented as level-crossing (LC) ADCs, but the circuits are area- and power-inefficient [1]. Asynchronous delta modulation, the original form of LC sampling, on the other hand can be compactly realized even in small pixels of vision sensors [4]. Traditional audio processing employs digital FFTs and BPFs after signal acquisition by high-precision ADCs. However, it has been shown in [5] that for classification tasks like voice activity detection (VAD), good accuracy can still be attained when filtering is performed using low-power analog BPFs. This paper presents a 0.5V 55µW 64×2-channel binaural silicon cochlea aiming for ultra-low-power IoE applications like event-driven VAD, sound source localization, speaker identification and primitive speech recognition. The source-follower-based BPF and the asynchronous delta modulator (ADM) with adaptive self-oscillating comparison for event encoding are highlighted for the advancement of the system power efficiency.