Jörg Kramer

Orientation-selective aVLSI spiking neurons

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

Light-emitting devices in industrial CMOS technology

Abstract Two different unmodified industrial CMOS processes have been used for the integration of highly interdigitated pn structures. Under forward bias these pn junctions emit narrow-band infrared light at 1160 nm with an electrical-to-optical power conversion efficiency of typically 10 −4 . The same junctions show broad-band visible-light emission between 450 and 800 nm in the avalanche breakdown region under reverse bias with efficiencies of the order of 10 −8 . This is already enough for a first few practical applications as light-emitting devices (LEDs). No satisfactory explanation for this emission efrect, fitting all the experimentally observed electro-optical and physical properties of our silicon LEDS, has been found yet.

Analog VLSI architectures for motion processing: from fundamental limits to system applications

This paper discusses some of the fundamental issues in the design of highly parallel, dense, low-power motion sensors in analog VLSI. Since photoreceptor circuits are an integral part of all visual motion sensors, we discuss how the sizing of photosensitive areas can affect the performance of such systems. We review the classic gradient and correlation algorithms and give a survey of analog motion-sensing architectures inspired by them. We calculate how the measurable speed range scales with signal-to-noise ratio (SNR) for a classic Reichardt sensor with a fixed time constant. We show how this speed range may be improved using a nonlinear filter with an adaptive time constant, constructed out of a diode and a capacitor, and present data from a velocity sensor based on such a filter. Finally, we describe how arrays of such velocity sensors call be employed to compute the heading direction of a moving subject and to estimate the time-to-contact between the sensor and a moving object.

Linear Systems Theory

This chapter contains sections titled: Linear Shift-Invariant Systems, Convolution, Impulses, Impulse Response of a System, Resistor-Capacitor Circuits, Higher Order Equations, The Heaviside-Laplace Transform, Linear Systems Transfer function, The Resistor-Capacitor Circuit (A Second Look), Low-Pass, High-Pass, and Band-Pass Filters

An integrated optical transient sensor

The implementation of a compact continuous-time optical transient sensor with commercial CMOS technology is presented. In its basic version, this sensor consists of a photodiode, five transistors and a capacitor. The proposed circuit produces several output signals in parallel. These include a sustained, logarithmically compressed measure of the incoming irradiance, half-wave rectified and thresholded contrast-encoding measures of positive and negative irradiance transients, and a signal that shows a combination of the sustained and the bidirectional transient response. The particular implementation reported in this work responds to abrupt irradiance changes with contrasts down to less than 1% for positive transients and 25% for negative transients. Circuit modifications leading to more symmetric contrast thresholds around 5% are also described. Due to their compactness these transient sensors are suitable for implementation in monolithic one- or two-dimensional imaging arrays. Such arrays may be used to sense local brightness changes of an image projected onto the circuit plane, which typically correspond to moving contours.

Compact integrated motion sensor with three-pixel interaction

An integrated circuit with on-chip photoreceptors is described, that computes the bi-directional velocity of a visual stimulus moving along a given axis in the focal plane by measuring the time delay of its detection at two positions. Due to the compactness of the circuit, a dense array of such motion-sensing elements can be monolithically integrated to estimate the velocity field of an image and to extract higher-level image features through local or global interaction.

A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation

We present a multi-chip neuromorphic system in which an address event representation is used for inter-chip communication. The system comprises an analog VLSI transient imager with adaptive photoreceptors, an analog VLSI motion receiver chip and a prototyping communication infrastructure which allows for programmability of connections between the elements on the two chips. We describe the properties of the two VLSI chips and of the communication infrastructure. To characterize the whole system, we present examples of connectivity tables which allow it to compute translational motion and expanding motion and show data from the transient detector array and motion receiver chips.

System implementations of analog VLSI velocity sensors

We present three different architectures that make use of analog VLSI velocity sensors for detecting the focus of expansion, time to contact and motion discontinuities respectively. For each of the architectures proposed we describe the functionality of their component modules and their principles of operation. Data measurements obtained from the VLSI chips developed demonstrate their correct performance and their limits of operation.

An analog VLSI velocity sensor

An integrated circuit that computes the velocity vector of a visual stimulus in one dimension is presented. The circuit combines optical sensors and associated electronics on a single silicon chip, processed with standard CMOS technology. The velocity is inferred from the time delay of the appearance of an image feature at two fixed locations on the chip. The circuit operates quite robustly for high-contrast stimuli over considerable irradiance and velocity ranges. With lower-contrast stimuli the output signal for a given velocity tends to decrease, while the direction selectivity is still maintained. The individual motion-sensing cells are compact, and they are therefore suited for use in dense 1D or 2D imaging arrays.

Improved ON/OFF temporally differentiating address-event imager

We have fabricated an improved version of an imager reported earlier (Kramer, J., Int. Symp. Circuits and Systems, vol.II, p.165-8, 2002), primarily by using a better pixel circuit and better layout principles. The new imager functions over 5 decades of background illumination and has much more symmetrical ON and OFF responses. This imager achieves massive redundancy reduction by temporally differentiating the image contrast. The ideal functions of the pixels are to compute the rectified derivatives /sup d///sub dt/(log I) = (dI/dt)/I, where I is the photocurrent in the pixel. The values of these derivatives are rectified and output as rate-coded events on the AER (address-event representation) bus. The 2.2 mm by 2.2 mm, chip was built in a 0.35 /spl mu/m 4M 2P CMOS process. The pixels are 40 /spl mu/m by 40 /spl mu/m and the array has 32 by 32 pixels, each with ON and OFF outputs. System power consumption is about 30 mA at 3.3 V.