Todd A. Cook

Ray casting architectures for volume visualization

Real-time visualization of large volume data sets demands high-performance computation, pushing the storage, processing and data communication requirements to the limits of current technology. General-purpose parallel processors have been used to visualize moderate-size data sets at interactive frame rates; however, the cost and size of these supercomputers inhibits the widespread use for real-time visualization. This paper surveys several special-purpose architectures that seek to render volumes at interactive rates. These specialized visualization accelerators have cost, performance and size advantages over parallel processors. All architectures implement ray casting using parallel and pipelined hardware. We introduce a new metric that normalizes performance to compare these architectures. The architectures included in this survey are VOGUE, VIRIM, Array-Based Ray Casting, EM-Cube and VIZARD II. We also discuss future applications of special-purpose accelerators.

A microprocessor-based implantable telemetry system

The design methodology of an intelligent system for implantable biotelemetry instruments based on a modular set of CMOS chips connected by a specialized serial bus is described. General system requirements are discussed, and an overview of the system is given. The design of the serial buses, custom microprocessor, bidirectional telemetry chip, and sensor interface is described. Clock requirements are considered.<<ETX>>

Hardware acceleration of n-body simulations for galactic dynamics

N-body methods are used to simulate the evolution and interaction of galaxies. These simulations are usually run on large-scale supercomputers or on very expensive full-custom hardare. This paper presents an alternative hardware method for acceleration of N-body simulations. The method yields a significant fraction of the performance of custom hardware and provides a great deal more flexibility. A protoype implementation is presented.

System-level specification of instruction sets

System-level design requires some sort of specification for a system at the level of abstraction of the system. When the system (or sub-system) is a processor, the appropriate level of abstraction is the instruction set. However, there are no good approaches for describing processors at this level. Nevertheless, this type of specification has a number of benefits: it is more concise (and thus less error-prone) than more general alternatives; it can be re-used in later re-implementations; and it provides support for software codesign through compiler-generators (which rely on higher-level abstractions than other techniques provide). Therefore, we have developed a methodology and an embodying language for specifying processors at the instruction set level.<<ETX>>

Acceleration of template-based ray casting for volume visualization using FPGAs

Volume visualization is used heavily to view simulated or collected data sets in such applications as medical imaging, computational fluid dynamics, and climate modeling. However, software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for interactive viewing. This paper discusses methods for low-cost, hardware acceleration of volume visualization using a PC-hosted FPGA board. Our methods focus on volume rendering approaches, since these techniques are widely used and are computationally expensive; our primary method uses a template-based, ray-casting algorithm. This hardware implementation is substantially faster than a software-only version running on the host PC.

A functional specification language for instruction set architectures

Application-specific programmable processing systems consist of not only a processor, but also the software that runs on it. In order to support development of such systems, a design environment must support both hardware and software development. Unfortunately, there are no specification languages for processors that are suitable for such dual use. Therefore, we have designed a functional-style language that is specifically intended for describing instruction sets; its functional nature allows it to describe the result that an instruction produces without having to specify the mechanism of operation. This property is key to allowing dual use of the specification, since it will not be biased towards either hardware or software development. We are constructing a design environment based on our language.<<ETX>>

From processor timing specifications to static instruction scheduling

We show how to derive a static instruction scheduler from a formal specification of an instruction-level parallel processor. The mathematical formalism used is SCCS, a synchronous process algebra for specifying timed, concurrent systems. We illustrate the technique by specifying a hypothetical processor that shares many properties of commercial processors (such as the MIPS or SuperSparc) including delayed loads and branches, interlocked floating-point instructions, resource constraints, and multiple instruction issue.

Signed-digit online floating-point arithmetic for FPGAs

Many potential applications for reconfigurable computing need the dynamic range provided by floating-point arithmetic. However, doing floating-point on FPGAs is difficult because of the large amount of hardware required, particularly for multipliers. Some limited success has been obtained through digit-serial implementation of IEEE floating-point multipliers, but the IEEE representation is not easily or efficiently implemented in serial form. Therefore, we have been exploring alternate number representations. Signed-digit representations have shown some promise, since their form lends them to serial computation, which consumes much less hardware than fully parallel approaches. We show how the signed-digit representation can be used to implement floating-point arithmetic, and we present prototype implementations using Altera FPGAs.

Low-cost hardware acceleration for volume visualization

Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.