Todd Bauer

Ge–Si separate absorption and multiplication avalanche photodiode for Geiger mode single photon detection

A Ge–Si separate absorption and multiplication avalanche photodiode (SAM-APD) is reported. The structure is grown using a low temperature in situ clean and epitaxy process, Tinsitu and Tepitaxy<∼460°C, resulting in a Ge layer with a dislocation density of ∼5×1010cm−2. The SAM-APD has a responsivity of 3.2×10−4A∕W (1310nm) and a dark current density at punch-through of 0.2mA∕cm2. In Geiger mode (GM) at 206K, the dark count rates (DCRs) are ∼280kHz, which is within an order of magnitude of DCR reported for InGaAs∕InP GM APDs despite the high defect density in the Ge.

Fabrication of Patterned Arrays with Alternating Regions of Aluminum and Porous Aluminum Oxide

Fabrication of patterned anodic aluminum oxide arrays using a dense layer of barrier aluminum oxide as the anodization mask is described. This fabrication process includes patterning of the aluminum film with a photoresist and brief anodization at a high voltage. The photoresist is then removed and the aluminum film is again anodized at a low voltage to grow porous aluminum oxide. Using this procedure, we are able to fabricate anodic aluminum oxide arrays on silicon wafers consisting of alternating regions of porous aluminum oxide and aluminum metal perpendicular to the silicon substrate.

Width of Anodization Mask Required to Preserve a Metallic Phase during Porous-Type Anodization of Aluminum-Copper Films

Patterned arrays with alternating regions of the metallic phase and porous aluminum oxide are fabricated by using a dense layer of barrier aluminum oxide as a mask for porous-type anodization of 99.5% Al and 0.5% Cu films. The pore curvature at the interface between the metallic phase and porous aluminum oxide is investigated as a function of anodization voltage. The degree of anisotropy, which is defined as a ratio between vertical and lateral propagation of pores, increases slightly as anodization voltage increases. The pore curvature compromises the mask transfer during anodization due to the lateral pore propagation under the anodization mask. For miniaturization of regions composed of Al-Cu, it is important to establish the width of anodization mask required to preserve the metallic phase between two regions of porous aluminum oxide. Our results show that a 2 μm wide anodization mask is necessary during porous-type anodization of 3 μm thick Al-Cu films at a chosen set of anodization conditions (40 V, 3% w/v H 2 C 2 O 4 , 5°C).

Silicon photonics platform for national security applications

We review Sandias silicon photonics platform for national security applications. Silicon photonics offers the potential for extensive size, weight, power, and cost (SWaP-c) reductions compared to existing III-V or purely electronics circuits. Unlike most silicon photonics foundries in the US and internationally, our silicon photonics is manufactured in a trusted environment at our Microsystems and Engineering Sciences Application (MESA) facility. The Sandia fabrication facility is certified as a trusted foundry and can therefore produce devices and circuits intended for military applications. We will describe a variety of silicon photonics devices and subsystems, including both monolithic and heterogeneous integration of silicon photonics with electronics, that can enable future complex functionality in aerospace systems, principally focusing on communications technology in optical interconnects and optical networking.

Frequency Trimming of Aluminum Nitride Microresonators Using Rapid Thermal Annealing

To transition aluminum nitride (AlN) microresonator filters into a manufacturable technology, accurate control of the resonator frequency across a wafer is required. This paper describes a postfabrication rapid thermal anneal approach to trim resonator frequency over 27000 ppm with an accuracy of 500 ppm. Measurements made on 22.4 MHz resonators indicate that the effect of annealing on the resonators saturates in 5 min and upshift the resonator frequency super linearly with temperature. We replicate the frequency trimming effect on hermetically sealed wafer level packaged devices to reduce the across-wafer frequency distribution from 22000 to 4000 ppm. We confirm that this postannealing technique is permanent by temperature cycling the resonators from 50°C to 125°C. This technique provides a method to trim AlN microresonator frequency overcoming effects such as thin film variations, which are inherent to microsystems fabrication.

Minimization of undercutting in electrochemical micromachining of patterned aluminum–copper films

Al–0.5%Cu films patterned with an anodization mask of barrier Al2O3 are micromachined by porous-type anodization followed by chemical dissolution of porous Al2O3. Electrochemical micromachining results in well-defined metallic pillars separated by micro-grooves. The trapezoidal shape of the pillars is due to the lateral pore propagation under the anodization mask. Regardless of undercutting, porous-type anodization shows a higher degree of anisotropy than mostly isotropic wet chemical etching. The vertical growth of pores is accelerated with respect to the lateral propagation of pores by increasing the voltage of porous-type anodization. Consequently, the lateral pore propagation is minimized and for ~3 µm thick Al–0.5%Cu films the etch factor increases from 2.6 to 4.3 when the voltage is increased from 20 V to 60 V. Comparing the results obtained with the micromachining of ~3 µm and ~10 µm thick films at the same voltage, the etch factor decreases as the depth of micro-grooves increases. The etch factor depends on the distribution of secondary current density at the pattern scale during porous-type anodization, which is defined by the anodization mask coverage. A higher degree of anisotropy of porous-type anodization (in comparison to wet chemical etching) allows for more accurate shape control of three-dimensional metallic microstructures.

Electrochemical Micromachining Porous-Type Anodization of Patterned Aluminum–Copper Films

Porous-type anodization of patterned ∼10 μm thick Al-Cu films results in microstructures with alternating regions of Al-Cu and porous Al 2 O 3 . The volumetric expansion of porous Al 2 O 3 is minimized by increasing the anodization solution temperature. The fidelity of the mask transfer (10 μm wide) is compromised by the lateral pore propagation under the anodization mask. The Al-Cu pillars formed after complete dissolution of porous Al 2 O 3 have a trapezoidal shape. The height of pillars is twice (8 μm) the distance corresponding to the lateral pore propagation (4 μm). In contrast to wet chemical etching, porous-type anodization of patterned Al-Cu films is not isotropic.

SOI-enabled MEMS processes lead to novel mechanical, optical, and atomic physics devices

Beginning in the mid-1990s, Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers to develop a radiation-hardened semiconductor process for sub-0.5mum geometries. Successfully radiation hardening SOI technologies enabled an in-house processing familiarity that exceeded our expectations by opening opportunities to improve other technologies. Rather than rely on a single SOI technology, we have developed families of SOI processes using SOI wafers specifically tailored for each of a number of diverse applications. From this SOI expertise, we have designed, developed, and fabricated a number of novel devices that exploit a variety of mechanical, electrical, and optical phenomena, including atomic-physics based devices. We present a high-level description of our SOI process technologies using product examples. Of particular note are a novel accelerometer, RF MEMS microresonators and contacting switches, integrated optics (low-loss Si waveguides, the smallest and lowest power micro-ring modulators and thermo-optic phase modulators/switches), and ion traps for quantum computing (along with other atomic physics device examples).

Front end of line integration of high density, electrically isolated, metallized through silicon vias

We have developed a complete process module for fabricating front end of line (FEOL) through silicon vias (TSVs). In this paper we describe the integration, which relies on using thermally deposited silicon as a sacrificial material to fill the TSV during FEOL processing, followed by its removal and replacement with tungsten after FEOL processing is complete. The uniqueness of this approach follows mainly from forming the TSVs early in the FEOL while still ultimately using metal as the via fill material. TSVs formed early in the FEOL can be formed at comparatively small diameter, high aspect ratio, and high spatial density. We have demonstrated FEOL-integrated TSVs that are 2 µm in diameter, over 45 µm deep, and on 20 µm pitch for a possible interconnect density of 250,000/cm2. Moreover, thermal oxidation of silicon can be used to form the dielectric isolation. Thermal oxidation is conformal and robust in the as-formed state. Finally, TSVs formed in the FEOL alleviate device design constraints common to vias-last integration.

Thermomechanical modeling of back-end-of-the-line 3D interconnects

Three-dimensional (3D) integrated circuits (ICs) offer considerable advantages over traditional 2D IC designs by offering increased signal speeds and lower operation power, and by combining multiple technology functions in a low-volume, stacked design. The design complexity of 3D ICs introduces an increased sensitivity of operation and reliability due to the thermomechanical interactions among their multilevel components. Therefore, physical modeling has become a critical task in the design phase of 3D ICs to manage and reduce these sensitivities, and to increase yield and reliability. In this paper, we develop and employ a high-fidelity, 3D finite element modeling framework to examine the thermomechanical response of 3D IC interconnects. We demonstrate attributes of our framework on a back-end-of-the-line via chain. First, we generate geometry using process definitions, develop a parameterized mesh, and identify material parameters from characterization experiments. Then, using advanced, massively parallel computational resources, we simulate fabrication steps to approximate the stresses and deformations experienced by the microstructure as a result of processing temperatures. Ultimately, our modeling approach provides a capability to assess the thermomechanical response of 3D IC components and provides a basis for designing structures robust to fabrication and processing variations.