Tohru Hara

Stress in Copper Seed Layer Employing in the Copper Interconnection

Stress of copper seed employing in the copper interconnection layer is studied. Since this stress affects largely the adhesion strength at the Cu/barrier layers and the Cu~111! orientation of copper layer, reduction of stress is important. Higher and high stresses are applied in the layer on TaN and Ta barrier layers. These layers can lead to poor adhesion strength. Much better adhesion strength can be accomplished in the layer on the TaSiN barrier layer. The surface changes to rough surfaces with annealing at 400°C in the layer deposited on TaN. The highly stressed layer changes to a low stress layer as a result of this agglomeration. However, a smooth surface is held in the low stress layer on the TaSiN barrier layer.

Properties of Copper Layers Deposited by Electroplating on an Agglomerated Copper Seed Layer

This paper describes the properties and adhesion strength of electroplated copper layers deposited onto two different seed layers. In a thin (10 nm) seed layer, which we term seed layer A, agglomeration occurs across the full thickness of the layer and a stress free or lower stress seed layer is formed with an annealing at 400°C. A highly (111)-oriented copper conductive layer is the result of this electroplating strategy. The adhesion strength is so high (40 gf) that no peeling occurs during chemical mechanical planarization (CMP) in this layer. When the layer is electroplated onto a thick (100 nm) seed layer, which we term seed layer B, agglomeration only occurs at the interface with Ta barrier layer with this annealing. Although a smooth copper layer still remains at the surface, a weakly (111)-orientated copper layer is electroplated. The adhesion strength of this type of copper layer is as low as 10 gf so that peeling can easily occur both during annealing and CMP. Correlation is found between the critical pressure defined by the pressure occurring of the peeling in the copper layers during the CMP with adhesion strength.

Improved Barrier and Adhesion Properties in Sputtered TaSiN Layer for Copper Interconnects

The barrier effect for copper diffusion and the adhesion properties of copper seed layers were studied for sputtered TaSiN layers. The diffusion depth of copper following 400°C annealing is as deep as 25 nm using conventional tantalum nitride (TaN) barrier layers. With the doping of Si in this layer to form TaSiN, the diffusion depth decreases drastically, reaching 5.0 nm for an optimum Si composition of 0.06-0.09 The stress of thin copper seed layers deposited on TaSiN is much lower than that on conventional Ta barrier layers, decreasing rapidly with increasing Si composition. There appears to be no agglomeration in the low stress copper seed layer. The highest adhesion strength is attained in a copper layer deposited on a TaSiN adhesion layer with a Si composition of 0.16. Note that the optimized Si composition is different between two layers, that is, the barrier and adhesion layers.

Control of the (111) Orientation in Copper Interconnection Layer

Low sheet resistance copper conductive layer has been used extensively in logic large scale integrated circuits. High density current can be flowed under the high stress field. Higher electromigration resistance is another promising point in the copper conductive layer. 1,2 Deposition of thick copper conductive layer with high ~111! orientation and with low stress is required in the copper conductive layer. 3 It has recently been reported that resistivity of the electroplating copper layer is determined mainly by the grain growth of ~111! and by the stress with barrier layer 4 rather than by the impurity in the copper layer. Adhesion strength of thick copper conductive layer and agglomeration of the copper seed layer are also influenced by the ~111! orientation and by the stress of seed layer as reported elsewhere. 5,6 Although the control of the ~111! orientation is very important in the copper conductive layer, few papers have reported the control of ~111! orientation in the electroplating layer. This paper describes the control of ~111! orientation in electroplating copper layer.

Electroplating of copper conductive layer on the electroless-plating copper seed layer

High resistivity and peeling have been problems with electroless copper layers preventing their use as a seed layer. Further, when copper is electroplated onto this seed layer, the resistivity is as high as 4.0 μΩ cm, much higher than the 2.2 μΩ cm value when plated on a physical vapor deposition (PVD) seed layer. This paper describes the deposition of low resistivity in copper conductive layer on the electroless-plating copper seed layer. The resistivity of the as-deposited layer decreases from 4.0 to 2.7 μΩ cm as the grain size increases from 33 to 42 nm. The grain size and resistivity of the copper layer correlate with the stress in the copper conductive layer and in seed layers. The grain growth can be enhanced by reducing the stress in the copper seed layer. A low stress and highly (111) oriented seed layer can be deposited with nucleation control. Stress reduction can also be achieved by employing the agglomeration process for the seed layer. A resistivity of 2.2 μΩ cm was attained in this conductive layer electroplated from copper hexafluorosilicate electrolytic solution on the low stress seed layer. This resistivity is comparable to the value obtained in a conventional electroplated copper layer on the PVD seed layer.

The Self-Annealing Phenomenon in Copper Interconnection

The variation of stress and resistivity with time, the phenomenon of self-annealing, is studied in a copper interconnection layer deposited by electroplating. In a conventional copper sulfate layer deposited on a TaN barrier layer, a high stress copper layer, the resistivity and stress are high and decrease rapidly with self-annealing. For example, the resistivity decreased from 2.9 to 2.4 μΩ cm as the stress fell from 33 to 28 MPa over 1 month. However, a self-annealing effect such as this cannot be observed clearly when low stress and low resistivity copper layers are deposited. Lower stress and lower resistivity copper layers may be deposited by electroplating in a copper hexafluorosilicate electrolytic solution. A self-annealing phenomenon cannot be observed in this layer.

Effect of Stress on the Properties of Copper Lines in Cu Interconnects

The effect of the stress and grain size of the seed layer deposited on TaN and Ta/TaN barrier films on the properties of electroplated copper interconnection layer is described. Properties such as resistivity and grain size are studied. The effect of chemicals employed for electroplating the copper layer is also studied after deposition on these seed layers. A lower resistivity copper layer can be obtained by reducing stress and by growing grain size in the seed and interconnection layers.

Ion implantation of arsenic in chemical vapor deposition tungsten silicide

Impurity profiles in arsenic implanted chemical vapor deposition (CVD) tungsten silicide (WSix) have been studied. Arsenic was implanted in WSi2.6 layer deposited on silicon substrates, and impurity profile measurements were performed by Rutherford backscattering spectrometry (RBS) techniques. Observed profiles in the as‐deposited silicide can be fitted well with calculated Gaussian distribution. Carrier concentration profile measurements of silicon substrates indicate that tailing of the profile due to a channeling did not occur. Therefore, a sufficient masking effect has been achieved by this layer for use in a self‐aligned gate implantation process. When annealing was done, the dissolution of excess silicon occurred from the nonstoichiometry silicide. Arsenic ion implanted into the silicide diffused into the silicon substrate. As a result, deeper junctions with a lower surface concentration is formed by furnace annealing. However, shallow junctions were formed by rapid thermal annealing (RTA).

Measurement of Adhesion Strength in Copper Interconnection Layers

The adhesion strength of copper layers on TaN barrier layers decreases from 19.5 to 10 gf with annealing at 400°C. A much lower stress layer can be obtained when a seed layer is deposited on a TaSiN barrier layer. The adhesion strength is as high as 35 gf and is not changed by annealing. The critical pressure for delamination at the barrier layer/low dielectric (e) layer interface decreases from 350 to 200 g/cm 2 when e is reduced from 3.3 to 2.7 in an SiOC interlayer. That is, better adhesion strength can be attained when an interlayer with a higher dielectric constant is used.

Resistivity of thin copper interconnection layers

Resistivity is observed quantitatively in a thin electroplated copper layer. A resistivity of 2.6 µΩcm is observed in a 600-nm-thick as-deposited copper layer by conventional electroplating. This resistivity increases rapidly with decreasing thickness and reaches 7.8 µΩcm at a thickness of 75 nm. This rapid increase is mainly due to the increase in the orientation ratio of the copper (111)/(200). The resistivity in the as-deposited layer is maintained at 2.2 µΩcm in a 75 nm low resistivity layer with a low orientation ratio. Such a low-resistivity thin layer is electroplated practically by newly developed process. The preparation of a low-stress seed layer is also required in this electroplating process.