Shiho Sasaki

Process development for EUV mask production

Absorber layer patterning process for low reflectivity tantalum boron nitride (LR-TaBN) absorber layer and chromium nitride (CrN) buffer layer were improved to satisfy high resolution pattern and high level critical dimension (CD) control. To make 100nm and smaller pattern size, under 300nm resist thickness was needed because of resist pattern collapse issue. We developed absorber layer dry etching process for 300nm thickness resist. Absorber layer patterning was done by a consequence of carbon fluoride gas process and chlorine gas process. We evaluated both gas processes and made clear each dry etching character. Sufficient resist selectivity, vertical side wall, good CD control and low buffer layer damage were obtained. Then, we evaluated how buffer layer dry etching affects EUV reflectivity. Finally, we evaluated EUV mask pattern defect inspection and defect repair. Sufficient contrast of mask pattern image and good repair result were obtained using DUV inspection tool and AFM nano-machining tool, respectively.

EUV-mask pattern inspection using current DUV reticle inspection tool

EUV mask pattern inspection was investigated using current DUV reticle inspection tool. Designed defect pattern of 65nm node and 45nm node were prepared. We compared inspection sensitivity between before buffer etch pattern and after buffer etch pattern, and between die to die mode and die to database mode. Inspection sensitivity difference was not observed between before buffer etch pattern and after buffer etch pattern. In addition to defect inspection, wafer print simulation of program defect was investigated. Simulation results were compared to inspection result. We confirmed current DUV reticle inspection tool has potential for EUV mask defect inspection.

Evaluation of dry etching and defect repair of EUVL mask absorber layer

EUVL mask process of absorber layer, buffer layer dry etching and defect repair were evaluated. TaGeN and Cr were selected for absorber layer and buffer layer, respectively. These absorber layer and buffer layer were coated on 6025 Qz substrate. Two dry etching processes were evaluated for absorber layer etching. One is CF4 plasma process and the other is Cl2 plasma process. Etch bias uniformity, selectivity, cross section profile and resist damage were evaluated for each process. Disadvantage of CF4 plasma process is low resist selectivity and Cl2 plasma process is low Cr selectivity. CF4 plasma process caused small absorber layer damage on isolate line and Cl2 plasma process caused Cr buffer layer damage. To minimize these damages overetch time was evaluated. Buffer layer process was also evaluated. Buffer layer process causes capping layer damage. Therefore, etching time was optimized. FIB-GAE and AFM machining were applied for absorber layer repair test. XeF2 gas was used for FIB-GAE. Good selectivity between absorber layer and buffer layer was obtained using XeF2 gas. However, XeF2 gas causes side etching of TaGeN layer. AFM machining repair technique was demonstrated for TaGeN layer repair.

Full field imprint masks using variable shape beam pattern generators

Imprint lithography has been included on the ITRS lithography roadmap at the 32, 22, and 16nm nodes. Step and flash imprint lithography (S-FIL®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100-nm feature resolution without the significant expense of multielement, high quality projection optics, or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For device manufacturing, one of the major technical challenges remains the fabrication of full field 1X templates with commercially viable write times. Recent progress in the writing of sub-40-nm patterns using commercial variable shape e...

PROGRESS OF NIL TEMPLATE MAKING

Nano-imprint lithography (NIL) has been counted as one of the lithography candidates for hp32nm node and beyond and has showed excellent resolution capability with remarkable low line edge roughness that is attracting many researchers in the industry who were searching for the finest patterning technology. Therefore, recently we have been focusing on the resolution improvement on the NIL templates with the 100keV acceleration voltage spot beam (SB) EB writer and the 50keV acceleration voltage variable shaped beam (VSB) EB writer. The 100keV SB writers have high resolution capability, but they show fatally low throughput if we need full chip writing. Usually templates for resolution pioneers needed just a small field (several hundred microns square or so), but recently requirements for full chip templates are increasing. For full chip writing, we have also started the resolution improvement with the 50keV VSB writers used in current 4X photomask manufacturing. The 50keV VSB writers could generate full chip pattern in a reasonable time though resolution limits are inferior to that with the 100keV SB writers. In this paper, we will show latest results with both the 100keV SB and the 50keV VSB EB writers. With the 100keV SB EB writer, we have achieved down to hp15nm resolution for line and space pattern, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50keV VSB EB writer, we have achieved down to hp22nm resolution for line and space pattern. Though NIL has excellent resolution capability, solutions for defect inspection and repair are not clearly shown yet. In this paper, we will show preliminary inspection results with an EB inspection tool. We tested an EB inspection tool by Hermes Microvision, Inc. (HMI), which was originally developed for and are currently used as a wafer inspection tool, and now have been started to seek the application for mask use, using a programmed defect template.

In-field CD uniformity control by altering transmission distribution of the photomask, using Ultra fast pulsed laser technology

As pattern feature sizes on the wafer become smaller and smaller, requirements for CD variation control has become a critical issue. In order to correct CD uniformity on the wafer, the DUV light transmission distribution of the photomask was altered using an ultra-fast pulsed laser technology. By creating a small scattering pixel inside the quartz body of the mask, a multitude of such points creates Shading Elements inside the quartz according to a predetermined CD variations distribution map. These Shading Elements reduce the dose of scanners laser illumination onto the wafer per a local area. Thus by changing the local light intensity, inside the exposure field, to a required level during the photolithographic process the wafer CD is changed locally inside the field. This complete process of writing a multitude of Shading Elements inside the mask in order to control the light transmission and hence wafer level CD locally is called the CD Control (CDC) process. We have evaluated the tool utilizing Ultra fast laser pulses (CDC 101) for local transmission and CD controllability on the wafer. We used Binary and Att-PSM test masks and three kinds of test patterns to confirm the sensitivity of transmission and CD change by the attenuation levels of Shading Elements which is sequentially changed from 0% to 10%. We will compare the AIMS results to printed CD on wafer or simulation results, so that we can correlate the transmission change and CD change by the attenuation levels. This paper also reports the CD uniformity correction performances by using attenuation mapping method on Binary mask. We also cover how Shading Elements affect the phase and transmission on the Att-PSM.

Development of attenuating PSM shifter for F2 and high-transmission ArF lithography

A new att-PSM shifter for both F2 and high-transmittance ArF lithography was developed. This shifter consists of SiON / TaHf in stacked layers. SiON for phase shift layer has a moderate transmittance and refractive index, and has sufficient laser durability. The TaHf film, which is a transmittance control layer, was effective as a functional layer in mask dry etching. Adopting the 3 step etching procedure, low damage of the quartz surface and less impact to CD shift was realized. It was confirmed that a new shifter has also sufficient feasibility to the mask inspection and repair process.

Study of mask process development for EUVL

EUVL mask process of absorber layer dry etching and defect repair were evaluated. TaGeN and Cr were selected for absorber layer and buffer layer, respectively. These absorber layer and buffer layer were coated on 6025 Qz substrate. Two dry etching processes were evaluated for absorber layer etching. One is CF4 gas process and the other is Cl2 gas process. CD uniformity, selectivity, cross section profile and resist damage were evaluated for each process. FIB-GAE and AFM machining were applied for absorber layer repair test. XeF2 gas was used for FIB-GAE. Good selectivity between absorber layer and buffer layer was obtained using XeF2 gas. However, XeF2 gas causes side etching of TaGeN layer. AFM machining repair technique was demonstrated for TaGeN layer repair.

Evaluation of multilayer damage in EUVL mask fabrication process

To obtain a high throughput and good CD uniformity, the EUV reflectivity of EUVL masks must be high and very uniform. In this study, EUVL masks were fabricated, and the degradation in EUV reflectivity due to the fabrication process was evaluated. The damage to the multiplayer due to plasma etching appeared as a drop in peak reflectivity of about 2.0%. Etching the Cr buffer layer by a wet process reduced the value to within the measurement error. On the other hand, thermal damage appeared as both a drop in peak reflectivity and a shift in centroid wavelength. The drop in peak reflectivity was about 0.5-1.0% in the temperature range 140-240° C, and about 1.5% in the temperature range 260-280°C. The shift in centroid wavelength increased monotonically as the temperature rose from 180degrees C to 280°C. To ensure good CD uniformity, both the shift and the variation in centroid wavelength should be kept within ∓0.02 nm. If a drop in peak reflectivity of 1-2% is acceptable, annealing could be an effective way to adjust the centroid wavelength by as much as 0.10 nm with an accuracy of ∓0.01 nm.

CD performance of CA-resits with dynamically controlled multizone bake system

CD-uniformity data of chemically amplified (CA) resists have been generated, by using a dynamically controlled multi-zone hotplate system, APB5000. The optimized baking procedure of the APB5000 system for Post Coat Bake (PCB) and Post Exposure Bake (PEB) is characterized by a maximum in the total temperature range on a 6025 mask substrate surface of 0.5 degree(s)C during the heat-up ramping and smaller than 0.2 degree(s)C at the set-point temperature of 90 degree(s)C. In this experiment CD-uniformity for isolated lines was improved to 7.8nm, compared to 13nm when using conventional baking systems. Additionally, a compensation method based on the baking processes is presented to further decrease the CD- uniformity range of CA-resists. Derived from CD-uniformity data measurements, a local temperature variation from the optimized baking strategy of the APB5000 system is used to compensate CD-errors caused by other process steps. In this experiment the result of such a measure showed a 40% improvement of the CD-uniformity range for dense lines from 14.2nm to 8.0nm.