Tokumichi Murakami

A DSP architectural design for low bit-rate motion video codec

A new digital signal processor (DSP) architecture is presented. This DSP consists of the usual components, such as instruction set, buses, data memories, execution unit, address generators, sequencer, and direct memory access controller, optimized for video signal processing. A 24-bit 50-ns DSP called the digital image signal processor (DISP) has been developed using 1- mu m CMOS technology. The performance of the DSP is evaluated by a benchmark test based on an actual video coding sequence. A multi-DSP configuration for a video codec that allows flexible algorithms and variable picture formats is studied. A low-bit-rate motion video codec can be built very easily using the DSPs presented by the authors. >

A DSP architecture for 64 kbps motion video codec

The authors describe an architectural study of a digital signal processor (DSP) well suited for video codec. This DSP consists of specified resources optimized for video signal processing, such as the instruction set, buses, data memories, execution unit, address generators, sequencer, and DMAC. The performance of the DSP is evaluated through several video coding sequences. The architecture of a multiprocessor configuration for video codec, which will allow flexible algorithm and variable picture format, is also examined.<<ETX>>

On Separate Color-Plane Prediction for Direct 4:4:4 Video Coding

In this paper, we propose a video coding scheme supporting direct 4:4:4 source format, which is designed as a straight-forward extension of MPEG-4 AVC/H.264 high profile coding. In the proposed scheme, each color component is encoded with independent spatio-temporal prediction using coding tools supported by MPEG-4 AVC/H.264 high profile, which is now regarded as the most powerful video compression standard in the world. We discuss the performance of the proposed method in comparison with several candidate schemes, and will show that the proposed scheme achieves coding performance improvement in terms of signal representation fidelity (PSNR) around higher bitrate range that is valuable for high quality applications. The presented scheme has been proposed to the MPEG-4 AVC/H.264 standardization body as a candidate technique for the new 4:4:4 video coding standard.

New Video Coding Scheme Optimized for High-Resolution Video Sources

This paper presents a design of new video coding scheme targeting substantial compression performance with reasonable complexity for next-generation high-resolution video sources. While it takes a conventional block-based MC+DCT hybrid coding approach that is suitable for hardware implementation of a high-resolution video codec, the proposed scheme achieved significant improvement of coding efficiency by introducing various technical optimizations in each functional block, especially allowing the use of larger blocks for motion compensation and transform than conventional standards. According to our experimental analysis, the proposed scheme achieves approximately 26% bit-rate savings on average compared to the state-of-the-art standard AVC/H.264 high profile. We also study the tradeoff between complexity and performance of the codec towards its standardization and implementation.

A 24 bit DSP for motion video codec and software development support system

The authors describe the architecture of a digital signal processor (DSP) well suited for motion video coding and its software development support tools. The DSP, named DISP (digital image signal processor), is image-coding oriented. It consists of several specified resources optimized for video signal processing, such as two-dimensional addressing and a combined arithmetic operation function. A simple and flexible video codec will be implemented with the DISP modules. The DISP software development support system, which consists of software support tools (assembler, linker and simulator) and a hardware support tool (hardware debugger), provides an interactive development environment.<<ETX>>

Scene adaptive vector quantization for image coding

The authors propose a scene-adaptive vector quantization (VQ) scheme based on component VQ which encodes an image block into three fundamental components: mean, gain, and index of normalized output vector. The scheme provides scene adaptability by incorporating a dynamic codebook which is successively self-generated through the intellectual coding process. The latest codebook set with learning function can be stored and used for subsequent VQ operations. A hierarchical fast search algorithm is derived from a structural combination of a fixed codebook and a dynamic one. Excellent coding performance is demonstrated through computer simulation.<<ETX>>

Super high-definition image handling system

We have developed a super high definition image handling system using new progressive technologies. The system supports the functions of display, editing, storage, transmission, and image compression for the images over 2 K by 2 K pixel resolution. A sufficient performance has been achieved in image handling speed and picture quality. The system is expected to be used in the areas of electrical publishing, biomedical imaging, electrical museum, image filing system, image communication system, and remote plant control system. This system will also be expected to be the next generation Hypermedia Platform.

Rate and quality control for full-field video compression around 10 Mbps

A coding scheme for interlaced video is investigated at rates around 10 Mb/s, with a view toward telecommunication-oriented application and simple implementation. An adaptive motion-compensated prediction scheme is studied. An adaptive arrangement of pixels within a block is then examined. It is shown that the adaptive approach permits effective control and provides a great improvement in picture quality over basic coding schemes.<<ETX>>