Hideo Ohira

A 50 ns video signal processor

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.<<ETX>>

Super high-definition image handling system

We have developed a super high definition image handling system using new progressive technologies. The system supports the functions of display, editing, storage, transmission, and image compression for the images over 2 K by 2 K pixel resolution. A sufficient performance has been achieved in image handling speed and picture quality. The system is expected to be used in the areas of electrical publishing, biomedical imaging, electrical museum, image filing system, image communication system, and remote plant control system. This system will also be expected to be the next generation Hypermedia Platform.