Tom Van Breussegem

A 1.65W fully integrated 90nm Bulk CMOS Intrinsic Charge Recycling capacitive DC-DC converter: Design & techniques for high power density

A fully integrated high power density capacitive 2∶1 step-down DC-DC converter is designed in a standard Bulk CMOS technology. The implemented converter can deliver a maximum output power of 1.65W on a chip area of 2.14mm2, resulting in a power conversion density of 0.77W/mm2. Besides the primary goal of high power density a peak power conversion efficiency of 69% is achieved. This for a voltage step-down conversion from twice the nominal supply voltage of a 90nm technology (2Vdd = 2.4V) to 1V. Both the design as the implementation techniques to achieve the resulting power density, are discussed.

A fully integrated gearbox capacitive DC/DC-converter in 90nm CMOS: Optimization, control and measurements

This paper presents a fully integrated capacitive DC/DC-converter with a gearbox type topology. By merging multiple topologies the output voltage range is increased. The dual loop digital control improves load regulation compared with a conventional hysteretic control and reduces ripple under low load operation. The converter was implemented in a 90nm CMOS technology and measurements are presented.

CMOS integrated capacitive DC-DC converters

Introduction.- Converter Topologies and Fundamentals.- Modeling and Design of Capacitive DC-DC Converters.- Noise Reduction by Multi-phase Interleaving and Fragmentation.- Control of Fully Integrated Capacitive Converters.- Monolithic Integration of DC-DC Converters in CMOS.- DC-DC Converter Prototypes.- Conclusions.

A monolithic 0.77W/mm 2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS

A fully integrated capacitive DC-DC converter reporting an output power of 1.65W in a standard 90nm Bulk CMOS process is realized. This converter implements a 2:1 voltage step-down conversion from twice the nominal technology supply voltage. Peak power conversion efficiency was measured to be 69%. The chip measures 2.14mm2 including 12nF implemented in standard available MOS capacitors. These baseline MOS capacitors, along with the introduced Flying Well approach and the Intrinsic Charge Recycling approach, result in a maximum power density of 0.77W/mm2. The converter is controllable through an on-chip voltage controlled oscillator (VCO) generating the clock signals for each of the 21 interleaved converter cores of this multiphase implementation. The implemented core interleaving allows for an output voltage ripple smaller than 8% of Vo without any dedicated output smoothing capacitor, saving die area and thus boosting the power density.

A 1.65 W fully integrated 90 nm bulk cmos capacitive DC-DC converter with intrinsic charge recycling

A fully integrated high power density capacitive 2:1 step-down DC-DC converter is designed in a standard CMOS technology. The converter implements the presented flying well technique and intrinsic charge recycling technique to deliver a maximum output power of 1.65 W on a chip area of 2.14 mm2, resulting in a power conversion density of 0.77 W/mm2 . A peak power conversion efficiency of 69% is achieved, leading to an efficiency enhancement factor of +36% with respect to a linear regulator. This is for a voltage step-down conversion from twice the nominal supply voltage of a 90 nm technology (2Vdd = 2.4 V) to 1 V.

A fully integrated 74% efficiency 3.6V to 1.5V 150mW capacitive point-of-load DC/DC-converter

Thanks to scaling, CMOS switches and integrated capacitors have increased in quality and density. This creates new opportunities in miniaturizing DC/DC-converters by integrating power drivers, as well as switches and reactive components on a single die. A 150mW fully integrated capacitive DC/DC-converter, with Multiphase Single Bound Hysteresis Control is presented. The converter achieves a peak efficiency of 77% and a full load efficiency of 74% for an output-input-voltage conversion ratio of less than 45%. It is the first fully integrated closed-loop operating converter fabricated in Bulk CMOS achieving these ratings.

Dual-output capacitive DC-DC converter with power distribution regulator in 90 nm CMOS

A fully integrated Dual-Output capacitive DC-DC converter providing a total output power of 1 mW is presented. The converter realizes both a 2/3 and a 1/3 voltage conversion, from 1.2 V to respectively 0.755 V and 0.32 V. A hysteretic controller regulates both output voltages, independently of the power distribution between both outputs. It achieves an efficiency of 68.6 % for the nominal case, and a maximum efficiency of 75.3 %. The validity of the developed model and used design strategy were verified by a test chip implemented in a 90 nm bulk CMOS technology.

A DMOS integrated 320mW capacitive 12V to 70V DC/DC-converter for LIDAR applications

A 320mW integrated switched capacitor DC-DC converter is realized in a 0.35µm DMOS high voltage technology. This 10 stage converter generates 70V from a 12V voltage supply, at a maximum efficiency of 85.5% per stage. An on-chip control system varies the clock frequency from 0 to 35.4MHz in order to regulate the output voltage at varying loads and supply voltages. Each of the stages uses an integrated capacitor of 74pF. The total area of the chip is 6mm2.

Converter Topologies and Fundamentals

To build a solid understanding of the capacitive conversion technique, this chapter introduces the fundamental characteristics of capacitive DC–DC converters.

DC–DC Converter Prototypes

This chapter gives an overview of a number of capacitive DC–DC converter prototypes. In addition to the theoretical background presented in the previous chapters, the prototypes illustrate the proposed techniques and the measurements demonstrate their performance.