Tom W. Kwan

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS

Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power <; 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It uses a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd input swing while utilizing a low-voltage transistor implementation for the core ADC.

A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer

A 13-ENOB, 5 MHz BW, 3.16 mW 3-bit continuous-time ΔΣ ADC sampling at 432 MHz is presented. For power efficiency, this design utilizes a hybrid feedback feed-forward loop topology with SAR quantizer, feed-forward compensated amplifiers, and push-pull DACs. Further power efficiency is gained by performing excess-loop-delay compensation (ELDC) using the SAR quantizer SC-DAC, which reduces power overhead from ELDC to a negligible level. A 94 dB SFDR is achieved through feedback-DAC calibration. The 0.066 mm2 design is fabricated in 28 nm CMOS and achieves FoMs of 36.4 fJ/step and 175.9 dB.

A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS

This paper presents a fourth-order Chebyshev high-pass filter (HPF) in 65 nm CMOS process with programmable gain and corner frequency to support ADSL and 5/6 band VDSL applications. The HPF improves noise performance by reducing the number of cascaded stages in the receive path and using capacitive feedback to minimize the total number of resistors in the filter. The choice of filter architecture and the optimization of the feedback structure reduce noise for a given total filter capacitance. It achieves a 70 dB MTPR and -161 dBm/Hz (2.8 nV/radicHz ) input-referred noise for ADSL mode. An IM3 of -80 dBc at 10 MHz is measured for VDSL mode. The HPF consumes 236 mW from 2.5 V power supply with active area of 3 mm2.

A 70dB MTPR integrated programmable gain/bandwidth 4th-order Chebyshev highpass filter for ADSL/VDSL receivers in 65nm CMOS

This paper presents a 4th-order Chebyshev HPF in 65 nm CMOS process with programmable gain and corner frequency to support ADSL and 5/6 band VDSL applications. The HPF improves noise performance by applying capacitive feedback and feedforward in the filter. It achieves a 70 dB MTPR and -161 dBm/Hz (2.8 nV/radicHz) input referred noise for ADSL mode. An IM3 of -80 dBc at 10 MHz is measured for VDSL mode.

A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS

A fourth-order Chebyshev high-pass filter (HPF) that achieves input-referred noise of 3 nV/√Hz, MTPR greater than 72 dB, and power consumption of less than 81 mW with 0.7 mm2 area in 28 nm CMOS is presented. Area and power reductions are realized via a mixed-signal filter topology.