Pieter Vorenkamp

Fully bipolar, 120-Msample/s 10-b track-and-hold circuit

Describes the design and experimental results of a fully bipolar track-and-hold (T&H) circuit for use in video applications. A fully differential, open-loop approach has been chosen in order to meet the specifications with respect to track-to-hold step, droop rate, and hold-mode feedthrough. In order to obtain maximum high-frequency performance, p-n-p transistors have been omitted from the design. The T&H circuit has been realized in a 3-GHz f/sub T/ bipolar production process with a minimum emitter size of 2*9 mu m/sup 2/. The die size is 0.25 mm/sup 2/, consuming 40 mW from a single 5-V power supply. Ten-bit performance has been measured up to 12-Msample/s full-Nyquist sampling rate. At 200 Msample/2, 8-b performance has been observed over the full-Nyquist band. >

A 12 b 50 M sample/s cascaded folding and interpolating ADC

The architecture of this 12 b ADC is based on a three-stage conversion, using cascaded folding and interpolating techniques. Compared to other multi-stage ADC architectures, folding and interpolating ADCs are based on non-linear analog pre-processing. This architecture is an attractive solution for high-resolution ADCs, as extremely linear circuit topologies are not required. To increase the resolution of folding and interpolating ADCs above the published 8 b examples, without raising the number of parallel input stages or the number of comparators in the fine-comparator, a cascaded folding and interpolating architecture is introduced. The ADC achieves 64 dB signal-to-noise ratio (SNR) and 75 dB spurious-free dynamic range (SFDR), while quantizing a 15 MHz full-scale input signal at 50 MSample/s. The 7.0 mm/sup 2/ ADC is fabricated in a 13 GHz, 1 /spl mu/m BiCMOS process and dissipates 300 mW from a single 5.0 V supply. The device is mounted in a standard 44-pin plastic package.

Fully-Bipolar 120 MHz, 10-bit Track & Hold Circuit

A multicenter controlled study was designed to test the hypothesis that a loading dose of an antidepressant could shorten the latency of its clinical efficacy. Three parallel groups of about 40 endogenous depressive inpatients received either a loading dose of milnacipran (300 mg daily for 2 weeks and 150 mg daily during the 2 following weeks), the standard regimen of milnacipran in severe depression (200 mg daily for 4 weeks), or fluvoxamine (200 mg daily for 4 weeks). The duration of the study was 4 weeks, with assessments at baseline and after 4, 9, 14, 21, and 28 days of therapy by means of Montgomery and Asberg depression scale (MADS), the Hamilton depression scale, the Clinical Global Impressions (CGI), and a checklist of symptoms and side-effects. Results showed very similar evolution in the 3 treatment groups. In addition, the level of side-effects did not exhibit significant differences among the treatment groups, except for excitement-nervousness and akathisia which were more frequently reported with fluvoxamine. These results do not support the usefulness of a loading dose of an antidepressant such as milnacipran. They demonstrate however that milnacipran can be given at a 300 mg daily dose from the very first day of treatment with an excellent tolerance.

A 1 Gs/s, 10b digital-to-analog converter

At the 8b level, digital-to-analog converter (DAC) sampling rates exceeding 500 Ms/s have been reported. However, new application areas such as direct digital synthesis (DDS) and high-resolution graphics systems call for 10b to 12b linearity at sampling rates of 250 MHz and beyond. In a GaAs technology a 12b, 1 Gs/s DAC system has been implemented at the expense of a total power consumption of 3 W. This paper presents a differential DAC combining both 10b linearity with a 1 Gs/s sampling rate using only 730 mW from a single -4.5 V supply. The die is 5.0 mm/sup 2/.<<ETX>>

A 10 b 50 MS/s pipelined ADC

Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.<<ETX>>