Tomás Lang

Increasing the number of strides for conflict-free vector access

Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. Both matched and unmatched memories are considered: we show that the number of strides is even larger for the latter case. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order.

Conflict-free access of vectors with power-of-two strides

An address mapping and an access order is presented for conflict-free access to vectors with any initial address and power-of-two strides. We show that for this conflict-free access it is necessary that the memory be unmatched and present an implementation for M=2T, where M is the number of modules and T the module latency. Moreover, the implementation allows the masking of the latency of the address calculation, of the mapper, and of the bus arbiter.

Matrix Computations on Systolic-Type Arrays

List of Figures. List of Tables. 1. Introduction. 2. Systolic-Type Arrays for Matrix Algorithms. 3. Regularization of Matrix Algorithms. 4. Realization of Fixed-Size Arrays. 5. Partitioning by Cut-and-Pile. 6. Partitioned Realizations Using Coalescing. 7. A Linear Pseudo-systolic Array. 8. Mapping Matrix Algorithms. 9. Summary and Further Research.

A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units

In this paper we present a method to implement one-dimensional Systolic Algorithms with data contraflow using Pipelined Functional Units. Some procedures are proposed which permit the systematic application of the method. The paper includes an example of application of the method to a one-dimensional systolic algorithm with data contraflow for QR decomposition.

CONFLICT-FREE STRIDES FOR VECTORS IN MATCHED MEMORIES

Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. In this paper, we extend these schemes to achieve this conflict-free access for several families. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. The hardware rcquired is similar to that for the access in order.

Review of Basic Number Representations and Arithmetic Algorithms

In this chapter we briefly review basic number representations and algorithms used in digital arithmetic. The treatment is very concise; readers that need a more detailed review should consult some of the references listed at the end of the chapter. More advanced algorithms as well as the implementations are the topic of later chapters.

Mapping Matrix Algorithms

We now consider the use of the multimesh graph method for mapping matrix algorithms onto existing application-specific array processors. The term application-specific indicates that the processing elements and the interconnection structure are basically well-suited for the class of matrix algorithms. However, since the underlying generality is achieved by having a large variety of features, it becomes necessary to adapt the method to those features.

Regularization of Matrix Algorithms

Several techniques have been proposed for the design of application-specific systolic arrays, seventeen of which were reviewed by Fortes et al. in [FFW88]; new ones have been proposed since then. Among the different approaches, the most successful one has been a transformational paradigm, wherein the description of an algorithm is successively transformed and made suitable for an implementation. In this chapter, we examine some issues regarding these transformational techniques. Moreover, we focus on the method that is the main topic of this book and introduce the regularization process in it.

Realization of Fixed-Size Algorithm-Specific Arrays

In this chapter, we have discussed the process of realizing the multi-mesh graph of an algorithm as an application-specific systolic-type array, for a problem of a given fixed size. We have presented a procedure for these purposes, which consists of grouping the nodes in the MMG by prisms, scheduling the nodes in each prism, and allocating each prism to one cell of an array. The proposed schedule of nodes consists of three nested loops, which takes advantage of the existence of transmitted data in a way that allows the efficient use of pipelined cells and of small fixed-size internal storage per cell. These aspects are directly related to the features of the pseudosystolic model of computation introduced in Chapter 2. Consequently, the multimesh graph makes it easy to obtain the characteristics of an implementation, including the array topology, the cell bandwidth, the internal storage and its organization. Moreover, the procedure allows the evaluation of performance and cost measures, as well as the evaluation of different tradeoffs that arise while deriving an implementation.

Systolic-Type Arrays for Matrix Algorithms

In this chapter, we describe an architectural model of processor arrays for matrix algorithms, including the different types of cells that can be used in such arrays. We refer to these architectures as “systolic-type” arrays because they use some of the features originally proposed for systolic structures [Kun82]. We first describe the issues arising during the process of implementing matrix algorithms as application-specific arrays, and summarize the design space as well as performance and cost measures for these computing structures. We also present the models of computation suitable for systolic-type arrays, and discuss the relationship among the size of matrices and arrays. Based on the concepts described here, the following chapters will present a method to implement matrix algorithms in systolic-type arrays.