Tomas Rokicki

Automatic Verification of Timed Circuits

This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on a behavioral semantics of timed trace theory. We present improvements to a geometric timing algorithm that take advantage of concurrency by using partial orders to reduce the time and space requirements of verification. This algorithm has been fully automated and incorporated into a design system for timed circuits, and experimental results demonstrate that this verification algorithm is practical for realistic examples.

Automatic synthesis of gate-level timed circuits with choice

This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Our procedure begins with a textual specification capable of specifying conditional operation, or choice. This specification is systematically transformed to a graphical representation which can be analyzed using an exact and efficient timing analysis algorithm to find the reachable stale space. From this state space, a timed circuit that is hazard-free at the gate-level is derived, facilitating the use of semi-custom components, such as standard-cells and gate-arrays. Because timing information is used to guide the synthesis to reduce circuit complexity while guaranteeing correct operation, the resulting timed circuit implementations are up to 40 percent smaller and 50 percent faster than those produced using other design methodologies.

On Net Modeling of Industrial Size Concurrent Systems

The paper discusses the modeling of OLTP (On-Line Transaction Processing) using colored Petri nets and the Design/CPN tool. We have performed industrial-sized simulation of tens of thousands of transactions running on databases with millions of records. OLTP applications were chosen because the OLTP workloads emphasize update-intensive database services with up to thousands of concurrent transactions per second. The goal of the experiment was to develop a methodology for the net modeling of OLTP-like applications with respect to the ability of different computer systems to meet the OLTP benchmarks requirements. The effort spent on the successful modeling of such large systems resulted in some methodological conclusions which required us to avoid straightforward approaches to the net modeling and to develop a combined technique of using nets together with embedded programming for simulation and analytical modeling.

Colored Petri net methods for performance analysis of scalable high-speed interconnects

Large concurrent or distributed systems have proven notoriously difficult to comprehend due to their combinatoric complexity. There is a clear need for thorough formal system modeling at all design stages. Ease of use and validation capability are important criteria in method selection. It is important that the selection permit evaluation of design details with respect to performance and behavioral goals. Net models are a likely candidate to achieve the requisite needs of such a modeling environment. They provide both graphical and mathematical system modeling views which inherently enable both quantitative and qualitative analysis of the design. To demonstrate this claim, a colored Petri Net model and performance analysis of a particular scalable multiprocessor interconnect fabric is presented. The fundamental component of this fabric is an adaptive routing device, R2. The R2 fabric is based on the interconnection scheme used in the Mayfly parallel processing system.<<ETX>>

The Hermod behavioral synthesis system

Hermod is an interactive behavioral synthesis program developed at Stanford University. Using a combined control and data flow graph (C/DFG) as an intermediate representation, Hermod generates functional blocks and their interconnection from L -havioral descriptions. Hermod supports a menu-driven interface, displaying the control and data flow graph with a set of legitimate dming-cus and its hardware representation. Emphasizing user participation, the system allows the user to control state partitioning and resource sharing through a graphical interface to explore the maximal design space. Written in an objectoriented language C++, Hermod generates a hardware representation in several minutes C from a behavioral description of practical size on a VAXstation H/GPX.