Tom Blank

A Survey of Hardware Accelerators Used in Computer-Aided Design

Hardware accelerators, or special-purpose engines, have been used in computer-aided design applications for nearly 20 years. In this time, roughly 20 machines have been built and tested specifically for such purposes as simulation, design rule checking, placement, and routing. Their uses are increasing, and the machines are becoming commercially available. This survey describes not only the machines but also their problems and limitations. It also gives comparative data on speed-up techniques and performance. Examples include a simulation machine that achieves roughly a million-times speed-up over a conventional 1-MIP mainframe and a very low cost machine for design rule checking that provides a 100-times improvement. These and other examples clearly demonstrate the viability of special-purpose engines.

Parallel logic simulation on general purpose machines

Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.<<ETX>>

A Parallel Solution Method for Large Sparse Systems of Equations

This paper presents a new distributed multifrontal sparse matrix decomposition algorithm suitable for message passing parallel processors. The algorithm uses a nested dissection ordering and a multifrontal distribution of the matrix to minimize interprocessor data dependencies and overcome the communication bottleneck previously reported for sparse matrix decomposition [1]. Distributed multifrontal forward elimination and back substitution algorithms are also provided. Results of an implementation on the Intel iPSC are presented. Up to 16 processors are used to solve systems with as many as 7225 equations. With 16 processors, speedups of 10.2 are observed and the decomposition is shown to achieve 67 percent processor utilization. This work was motivated by the need to reduce the computational bottleneck in the Stanford PISCES [2] device simulator; however, it should be applicable to a wide range of scientific and engineering problems

A Parallel Bit Map Processor Architecture for DA Algorithms

Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing architecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability. Also included in this paper are descriptions of algorithms that exploit the architecture. Algorithms for routing, DRC, and bit vector manipulation are included.

A Best-First Search Algorithm for Optimal PLA Folding

In this paper we propose a new algorithm for optimal PLA folding based on a graph theoretic formulation. An efficient best-first search (BFS) algorithm is presented which finds a near-optimal PLA folding. The proposed algorithm first constructs the longest paths on the associated disjoint graph generated from the PLA personality matrix, and then extracts the ordered folding sets from the constructed paths. The algorithm is shown to be effective for most test cases.

Fast functional simulation: an incremental approach

In an effort to speed up simulation, a novel algorithm,, called incremental simulation evaluates the circuit components that can be affected directly or indirectly by design changes, utilizing the information generated during the previous simulation to reduce the number of component evaluations to a minimum. The authors describe the design and implementation of the incremental algorithm for logic or functional simulation, which substantially improves the run-time performance over existing simulators by using the incremental property of the hardware design process. >

Incremental-in-time algorithm for digital simulation

The authors present an incremental-in-time algorithm for incremental simulation of digital circuits. In contrast to the incremental-in-space algorithm, which pessimistically resimulates the circuit components that could be affected by design changes throughout the simulation time frames, the incremental-in-time algorithm resimulates a circuit component only for the simulation time frames when its inputs or internal state variable make different state transitions from the previous simulation run. It maximally utilizes the past history, thereby reducing the number of component evaluations to a minimum. Experimental results obtained for several practical circuits show speedups up to 30 times faster than conventional event-driven stimulation.<<ETX>>

The Hermod behavioral synthesis system

Hermod is an interactive behavioral synthesis program developed at Stanford University. Using a combined control and data flow graph (C/DFG) as an intermediate representation, Hermod generates functional blocks and their interconnection from L -havioral descriptions. Hermod supports a menu-driven interface, displaying the control and data flow graph with a set of legitimate dming-cus and its hardware representation. Emphasizing user participation, the system allows the user to control state partitioning and resource sharing through a graphical interface to explore the maximal design space. Written in an objectoriented language C++, Hermod generates a hardware representation in several minutes C from a behavioral description of practical size on a VAXstation H/GPX.

Hermod: an interactive behavioral synthesizer for VLSI

Hermod is an interactive behavioral synthesis program. Using a combined control and data-flow graph (C/DFG) as an intermediate representation. Hermod generates functional block representations from behavioral descriptions. Hermod supports a menu-driven interface, displaying the hardware representation for a particular state partitioning. Encouraging user participation in the synthesis process, the system allows the user to control state partitioning and resource sharing through a graphical interface to explore the maximal design space. In developing Hermod, emphasis was also placed on the systems capability to provide an easy verification of system-generated designs. Written in the object-oriented language C++, Hermod generates a hardware representation in several minutes from a behavioral description of practical size on a VAXstation II.<<ETX>>