Tomasz Bieniek
Warsaw University of Technology
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Publication
Featured researches published by Tomasz Bieniek.
international conference mixed design of integrated circuits and systems | 2007
P. Janus; Tomasz Bieniek; A. Kociubinski; P. Grabiec; Gerold Schröpfer
In this paper we present a system-level, top-down design/modeling methods for microsystem (MEMS) devices. We describe advanced process co-simulation/emulation of MEMS and integrated circuits. The methodology of hardware-in-the-loop basing on co-simulation of MEMS and IC using signal flow simulators is also discussed.
Microelectronics Journal | 2014
Grzegorz Janczyk; Tomasz Bieniek; J. Wasowski; P. Grabiec
Abstract This paper is the ongoing research report and discusses important aspects of new investigation method selected for interconnects reliability and ageing which has to be considered in nano-scale. The research is ongoing and applies to heterogeneous device structures like SiP, SoC where mechanical stress caused by thermal cycling, heat dissipation, assembly technique etc. distributes inside thin layers of metal interconnects.
international conference mixed design of integrated circuits and systems | 2007
Grzegorz Janczyk; Tomasz Bieniek; P. Janus; A. Kociubinski; P. Grabiec; J. Szynka; M.S. Reitz; P. Schneider; E. Kaulfersch; J. Weber
The complex silicon systems formed by the several specialized devices like SOC, RF devices, power devices, MEMS wafers are fabricated in dedicated technologies. If the designer attempts to integrate them into the one big multifunctional system, he meets the new, yet unexplored fields for the multidisciplinary, mutually dependent thermal, electrical, EM and mechanical parameters modeling. This article attempts to clarify, and presents how to simplify this problem.
ieee international d systems integration conference | 2014
Andrzej Kociubiński; Mariusz Duk; Tomasz Bieniek; Grzegorz Janczyk; Michal Borecki
This paper describes the fabrication of 3D-stacked, dual-band sensitive device and their preliminary characterization results. The device consists of two 3D integrated detectors. The square chip with fabricated 4H-SiC p-i-n junction was mounted on commercial silicon chip with large area VIS-photodiode made by Institute of Electron Technology in Warsaw. The UV-photodetector was made on n-type 4H-SiC substrate with a double epitaxial layer in which aluminum was implanted to form a p-n junction close to the surface, and a silicon dioxide layer was formed for passivation, without a guard ring. The optical and electrical characterization of each of the photodiode structures has been discussed including dark current and spectral response measurements of large-area silicon diode with 4H-SiC p-i-n junction. All the diodes showed excellent rectification with low leakage current.
ieee international d systems integration conference | 2014
Tomasz Bieniek; Grzegorz Janczyk; Magdalena Ekwińska; T. Budzynski; G. Gluszko; P. Grabiec; A. Kociubinski
The fundamental principle of complex systems development consists in integration of a range of design activities related to a set technological processes into the advanced, multistage, time consuming product development chain. The most representative sample smart system includes at least micro-electro-mechanical module (MEMS) assisted by the dedicated readout circuitry (IC) supporting specific signal conversion and data processing capabilities. Communication modules can be integrated in the IC or belong to particular application environment scheme.
ieee international d systems integration conference | 2013
Tomasz Bieniek; Grzegorz Janczyk; Rafał Dobrowolski; Dariusz Szmigiel; Magdalena Ekwińska; P. Grabiec; Janus Pawel; Jerzy Zajac
This paper discusses important aspects of development process of dedicated test vehicles designed for investigation on thin metal layers reliability by a novel Accelerated Thermo-Mechanical Ageing method (ATMA) [1] being developed now. It is an ongoing research report presenting current state of the R&D works, investigation on ATMA usefulness and its applicability to interconnect reliability evaluation.
Microelectronics Reliability | 2008
Grzegorz Janczyk; Tomasz Bieniek; J. Szynka; P. Grabiec
The fast development of device fabrication technology stimulates new challenging technology development and progress in wafer processing, module interconnections and packaging technology. Apart from a broad hardware experience, standalone software design simulations before a hardware fabrication are a necessity. This paper discusses software issues of the design and an experimental attempt to the device description and the device description data transfer.
2008 14th International Workshop on Thermal Inveatigation of ICs and Systems | 2008
Grzegorz Janczyk; Tomasz Bieniek; P. Grabiec; J. Szynka
Vertical chip integration applied in heterogeneous systems is a design approach used to extend the device functionality and improve its performance. Apart from the design advancements, thermal budget of the device is constrained internal structure of the device. Internal module components limit the efficiency of device cooling. It is one of the most important concerns of vertical integration reliability. Development of vertically integrated devices requires cooperation of different partners and designers. This paper presents thermo-mechanical simulation needs and capabilities. The presented HDL approach is used for thermal modeling of the structure and high level, NDA-proof thermal simulations of modules of stacked, heterogeneous devices.
Journal of Wide Bandgap Materials | 2001
Tomasz Bieniek; Andrzej Wojtkiewicz; Lidia Lukasiak; Romuald B. Beck
Two different methods of ultrathin oxide formation are studied here, classical thermal oxidation and Grilox (see Borsoni et al., Microelectronics Reliability). It was proved that the quality of the passivating layer has a crucial influence on the overall properties of the gate stack in all cases, for the well established technology of Si/sub 3/N/sub 4/, as well as for HfO/sub 2/ (still under investigation). The interface trap density distributions in the Si forbidden gap for exemplary test devices are presented.
Archive | 2016
Magdalena Ekwińska; Tomasz Bieniek; Grzegorz Janczyk; Jerzy Wąsowski; P. Janus; P. Grabiec; Grzegorz Głuszko; Jerzy Zajac; Daniel Tomaszewski; Karina Wojciechowska; Rafał Dobrowolski; Tadeusz Budzyński
This article is an attempt to describe design and verification process of the MEMS+IC (micro-electro-mechanical system assisted by an integrated readout circuit) structure designed in Institute of Electron Technology (ITE) dedicated for specific industrial microphone application. Design tools and methods are presented in this paper along with results of numerical simulations compared with real measurements performed for the key steps of device development.