Romuald B. Beck

Modeling of SOI-MOS capacitors C-V behavior: partially- and fully-depleted cases

A model is presented for the C-V characteristics of partially-depleted (PD) and fully-depleted (FD) SOI-MOS capacitors. The proposed model is flexible, allowing introduction of all types of nonidealities typical to MOS type structures. New formulae for the low- and high-frequency capacitances of these structures are derived. Due to the various charges stored in these structures, unusual and more complex C-V curves are obtained. C-V curves where interface-state densities have been individually introduced (one at a time) at all three SiO/sub 2/-Si interfaces of the SOI-MOS-C are also demonstrated. The model has been validated by fitting the predicted HF C-V curves for SOI-MOS-C and its inherent structure, the SIS capacitor, to the experimental data. The extracted electrophysical parameters of the studied structures, for both PD and FD cases, are very close, if not the same as the values determined during their fabrication.

Application of plasma enhanced chemical vapor deposition silicon oxynitride layers in nonvolatile semiconductor memory devices

In this paper, the authors present the new double gate dielectric structure for the nonvolatile semiconductor memory (NVSM) devices which is based of hafnium dioxide (HfO2). The novelty of this structure relays on the introduction of ultrathin silicon oxynitride (SiOxNy) formed by plasma enhanced chemical vapor deposition (PECVD). Fabricated test structures with the PECVD layers show repetitious behavior of the hysteresis characteristics in comparison to structure with silicon dioxide as the tunnel (bottom) dielectric, which the stability of hysteresis loop is observed after completing first stressing loop. Moreover, the memory window expressed as the flat-band voltage shift versus stress voltage is very wide (1.68V) and the maximum charge which can be stored by the double gate dielectric stack is of the order of 6×1012(cm−2). Comparison of current density versus gate voltage characteristics of investigated metal-insulator-semiconductor systems demonstrated significantly a decrease of the leakage current ...

PECVD formation of ultrathin silicon nitride layers for CMOS technology

The aim of this study was to check experimentally the feasibility of processing ultrathin Si 3 N 4 layers by low-temperature deposition of quality allowing in the future their application as the gate dielectric. The layers were grown in PECVD planar electrodes, RF plasma system. The optimisation of the technology was performed in order to obtain good reproducibility and control of the deposition process for ultrathin layers (thickness < 6 nm). The properties of the layers were studied by optical and electrical methods. The spectroscopic ellipsometry was used to determine the thickness and optical properties (e.g. refractive index) and check for any nonuniformity within the deposited layers. The test structures containing MOS capacitors and MOSFETs of different sizes with PECVD Si 3 N 4 layers as the gate dielectric were manufactured in order to perform electrical characterisation. Apart from the classical approach (C- V, I- V characteristics) the charge pumping technique has been also used to characterise the nitride-silicon interface. The obtained results have proved successful in the process optimisation effort and reasonably good (comparing to that in recent publications) properties of the formed system.

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO2) layers for non-volatile semiconductor memory (NVSM) applications

Abstract In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO x N y ) as the pedestal layer and hafnium dioxide layer (HfO 2 ) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO x N y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO x N y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.

Effect of carbon on thermal oxidation of silicon and electrical properties of SiO 2 -Si structures

Growth of thermal oxide on silicon implanted with carbon at low energies is studied and electrical characteristics of the resulting SiO2-Si structures are evaluated. After excluding the effect of surface damage on the oxide growth kinetics, it was determined that for the carbon implant doses up to 1014 cm−2 the effect on oxide growth kinetics is limited. At higher carbon doses significant retardation of oxide growth was observed. A clear correlation between carbon dose and electrical characteristics of SiO2-Si structures has also been established. In the case of each parameter of concern in this study its degrActation with increased carbon dose above 1014cm−2, which corresponds to carbon concentration in silicon of the order of 1019 cm3, was observed. These effects may come to play during thermal oxidation of silicon wafers subjected prior to oxidation to the reactive ion etching in carbon containing gases such as CF4, CHF3, and others.

Formation of ultrathin silicon oxides—modeling and technological constraints

Abstract The “ITRS Roadmap” suggests the necessity of constant reduction of dielectric thickness for a number of important applications in ICs technology. The technology of ultrathin layers is, however, very difficult. So is modeling. During the last two decades a number of theoretical models of silicon oxidation, based on different approaches and assumptions, were constructed in order to surpass limitations of the commonly used Deal–Grove model. They will be critically reviewed and discussed in this paper. More attention will be paid to Beck–Majkusiak model, which gives precise predictions even for ultrathin oxide thickness regime, for both: classical oxidation in furnace, and for processing in RTO reactor, and is consistent with description of plasma oxidation process. Some problems of modeling result from technological constraints or measurement methods available. These issues are also briefly addressed in this paper.

Effect of radiation on breakdown of electrically pre-degraded oxides in MOS structures

Abstract The influence of ionizing radiation on the dielectric strength and wear-out of electrically pre-degraded MOS structures is investigated. It is shown that irradiation significantly increases the number of defect-related failures in pre-degraded oxides, while does not affect an “intrinsic” dielectric strength. The observed effect increases as the amount of damage due to pre-irradiation F-N stress increases.

Investigation of double barrier MOS tunnel diodes with PECVD silicon quantum well

Abstract Double barrier metal–oxide–semiconductor tunnel diodes with ultrathin PECVD Si and thermal SiO 2 layers were fabricated. The measured capacitance–voltage and current–voltage characteristics were interpreted and physical parameters of the structures were extracted by means of a theoretical model.

Silicon Oxynitride Layers Fabricated by Plasma Enhanced Chemical Vapor Deposition (PECVD) for CMOS Devices

This work is devoted to the technology and characterization of silicon oxynitride layers (SiOxNy) formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). In the course of this work thermal stability of deposited layers was also examined. Expected changes in structure, chemical composition and electro-physical properties of the obtained layers were investigated by means of spectroscopic ellipsometry (SE), X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS) and electrical characterization of manufactured test structures (metal-insulatorsemiconductor (MIS) capacitors and MISFETs). Selected process parameters were chosen to fabricate SiOxNy layers which were introduced into MIS devices with double gate dielectric stack (based of hafnium dioxide). Electrical characterization of such MIS structures with PECVD silicon oxynitride have shown a feasibility of application of obtained system in non-volatile semiconductor memory (NVSM) devices.

Formation of ultrathin silicon layers by PECVD and their modification for nanoelectronic and nanophotonic applications

Nanoelectronic and nanophotonic applications have created a pressure on methods of fabrication double dielectric barriers stacks with ultrathin silicon layer located between dielectric layers. Among numerous possible methods, PECVD seems to be very promising. In order to increase possible number of applications, however, the ability to transform continuous silicon layer into nanocrystalline form in dielectric matrix is required. The work described below reports on experimental efforts to form such a structure by controlled high temperature recrystallization and oxidation of ultrathin PECVD silicon layer in the stack. The effects if high temperature annealing has been studied by spectroscopic ellipsometry. The applied model allowed for identification of composition and structural changes within the silicon PECVD layer due to different high temperature annealing processes applied. As a result of this study, it has been proved that it is feasible to fabricate complete two barrier stack consisting of ultrathin dielectric and silicon layers in one PECVD system without exposing samples to the ambient atmosphere. In order to reduce the PECVD silicon layer thickness to approximately 3 nm, we proposed using plasma oxidation in PECVD instead of PECVD oxide deposition. High temperature (especially in 1100°C) annealing in argon proved to allow formation of silicon nanocrystals in oxide matrix. Other effects resulting from high temperature annealing of fabricated stacks are also studied.