Tommaso Vali

A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s

In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.

A new low cost fingerprint recognition system on FPGA

This paper describes a new approach to fingerprint recognition problem, proposing a low cost system, implemented by FPGA. The work done shows the feasibility of having a miniaturized device, thanks to an ad-hoc architecture design, that can be embedded in the sensor. This kind of system has therefore the advantage to be an object with a high degree of diffusion, through the implementation by a reduced cost hardware (like entry-level FPGA). The proposed system maintains the same identification rate of classic solutions, but with best response time perceived at user, thanks to a new algorithm, based on binary operations and developed in order to lighten the computational architecture effort, at the expense of information redundancy in the database. The architecture has been organized with a high parallelism degree to handle information overhead and ensure a very fast response time. Features (specialized information) extraction is obtained by spatial binary filtering. Matching step is based on Euclidean distance between features vectors. A first prototype has been implemented on the Xilinx Virtex 4 Evaluation Board and tested with positive results. The new system shows an identification user rate greater than 97% and a performance improvement of 3 orders of magnitude, in comparison to the test environment set up as reference. The computational hardware cost can be further reduced, because the architecture is scalable towards inexpensive FPGA devices like Xilinx Spartan family, without losing improvement of response time.

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.

Full-wave modeling of inductive coupling links for low-power 3D system integration

In recent years, 3D system integration has emerged as a new paradigm to reduce the overall size of multichip systems (processor and memory stacks), improve data throughput, and lower assembly costs. Among the various techniques developed to connect multiple die in a 3D integrated-circuit (IC) package, inductive coupling links are very cost-effective solutions that require no specialized processing steps. While it is easy to use integrated inductors to implement inductive coupling links in standard CMOS processes, evaluating their electrical characteristics requires using an electromagnetic field solver software. And, integrating these links into a standard SPICE-like circuit design environment is not straightforward. In this paper, we describe a technique, based on the partial element equivalent circuit (PEEC) method, to model an integrated inductive coupling link as a simple lumped parameter circuit. Starting from layout and technology data, the lumped parameter circuit model can be used in a SPICE-like simulator for system design purposes.