Luca De Santis

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.

Full-wave modeling of inductive coupling links for low-power 3D system integration

In recent years, 3D system integration has emerged as a new paradigm to reduce the overall size of multichip systems (processor and memory stacks), improve data throughput, and lower assembly costs. Among the various techniques developed to connect multiple die in a 3D integrated-circuit (IC) package, inductive coupling links are very cost-effective solutions that require no specialized processing steps. While it is easy to use integrated inductors to implement inductive coupling links in standard CMOS processes, evaluating their electrical characteristics requires using an electromagnetic field solver software. And, integrating these links into a standard SPICE-like circuit design environment is not straightforward. In this paper, we describe a technique, based on the partial element equivalent circuit (PEEC) method, to model an integrated inductive coupling link as a simple lumped parameter circuit. Starting from layout and technology data, the lumped parameter circuit model can be used in a SPICE-like simulator for system design purposes.