Tomoaki Yoshizawa
Renesas Electronics
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Publication
Featured researches published by Tomoaki Yoshizawa.
IEEE Journal of Solid-state Circuits | 2004
Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade
In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.
international conference on computer aided design | 2005
Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara
6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.
international solid-state circuits conference | 2004
K. Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; S. Imaolka; Hiroshi Makino
A high-density dual-port SRAM (DP-SRAM) with a 2.04 /spl mu/m/sup 2/ cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%.
custom integrated circuits conference | 2001
Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shinichi Hattori; Atsushi Koshio; Kazuhiro Tsukamoto; Tetsuva Matsumura
A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.
international conference on microelectronic test structures | 2007
M. Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; N. Takeshita; Naofumi Murata; Tomohiro Tanaka; T. Fujiwara; K. Asahina; Masakazu Okada; Kazuo Tomita; Masahiko Takeuchi; Hirofumi Shinohara
We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.
IEICE Transactions on Electronics | 2008
M. Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; Tomohiro Tanaka; Takanari Fujiwara; Kyoko Asahina; Masakazu Okada; Kazuo Tomita; Masahiko Takeuchi; Shigehisa Yamamoto; Hiromitsu Sugimoto; Hirofumi Shinohara
We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.
Archive | 2003
Tomoaki Yoshizawa; Koji Nii; Susumu Imaoka
Archive | 2014
Yoshihiro Funato; Toshio Kumamoto; Tomoaki Yoshizawa; Kazuaki Kurooka
Archive | 2004
Tomoaki Yoshizawa
Archive | 2004
Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Hiroshi Makino