K. Nii

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mum2 and 0.327 mum2 were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead.

A 90nm dual-port SRAM with 2.04 /spl mu/m/sup 2/ 8T-thin cell using dynamically-controlled column bias scheme

A high-density dual-port SRAM (DP-SRAM) with a 2.04 /spl mu/m/sup 2/ cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%.

A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bitline equalizing technique improves the write margin whenever a write-disturb occurs. This technique is applicable for both synchronous and asynchronous clock frequencies between ports. We designed and fabricated a 256 kb DP-SRAM macro using 28-nm low-power CMOS technology and achieved low-voltage operation at 0.66 V and 1.4 ns write access time at 25°C, which are 120 mV lower and 40% faster than the conventional performance.

High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.

A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32/spl times/24-bit multiplier-accumulator was constructed using this new method. 540 um/spl times/840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.