Tomohiro Takahashi

Single-chip 5.8GHz DSRC transceiver with dual-mode of ASK and Pi/4-QPSK

We have developed a fully integrated 0.25 mum SiGe-BiCMOS transceiver with a power amplifier (PA), transmit / receive switch (T/R SW), orthogonal modulator / demodulator, received signal strength indicator (RSSI), and phase locked loop (PLL) for Dedicated Short Range Communications (DSRC) mobile terminals with Amplifier Shift Keying (ASK) and Pi/4- shifted Quadrature Phase Shift Keying (Pi/4-QPSK) dual-mode modulation. Transmitter architecture is based on the sliding-IF topology using 4.6 GHz VCO and a 1/4 divider. Receiver architecture is based on the fixed-IF super-heterodyne. For image spurious rejection in the transmitter, a passive band elimination filter (BEF) comprised of a differential inductor is implemented. The 3.1mm x 2.97 mm die is packaged in 5.8 mm x 5.8 mm 48 pin- VQFN.

A low voltage (1.8V) operation triple band WCDMA transceiver IC

A highly integrated triple band (800MHz/1.7GHz/2.1GHz) WCDMA transceiver IC which operates at low voltage (1.8V) is described. All functionalities are implemented in a single chip using a 0.18mum SiGe BiCMOS process. The direct conversion receiver consists of triple band preamplifiers, I/Q demodulators, channel select filters, and PGAs. The direct transmit upconverter consists of a modulator, a three stage VGA, and triple PA drivers. No TX carrier leakage calibration is needed. Two synthesizers with automatically calibrated VCOs are fabricated on the same chip. The IC draws 35mA in receive and 39-61 mA in transmit using a 1.8V supply voltage

A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture for region control

A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 4.2e-rms readout noise. An intelligent sensor system with face detection and high resolution region-of-interest (ROI) output is demonstrated with significantly low data bandwidth and low ADC power dissipation by utilizing a flexible area access function.