Katsuhiko Hanzawa

A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous

This paper presents a 400H×256V pixel CMOS image sensor including 128 on-chip memory/pixel with 1Tpixel/s in burst operation without cooling and 780Mpixel/s in continuous operation. To improve the read-out speed from the chip, a noise-reduction circuit in pixel and relay buffers is introduced.

A wide dynamic range CMOS image sensor with 200–1100 nm spectral sensitivity and high robustness to UV right exposure

A highly UV-light sensitive and sensitivity robust CMOS image sensor with a wide dynamic range (DR) was developed and evaluated. The developed CMOS image sensor includes a lateral overflow integration capacitor in each pixel in order to achieve a high sensitivity and a wide DR simultaneously. As in-pixel photodiodes (PDs), buried pinned PDs were formed on flattened Si surface. The PD has a thin surface p+ layer with a steep dopant concentration profile to form an electric field that drifts photoelectrons to the pinned n layer. This structure improves UV-light sensitivity and its stability. In addition, a buried channel source follower driver was introduced to achieve a low pixel noise. This CMOS image sensor was fabricated by a 0.18-µm 1-polycrystalline silicon 3-metal CMOS process technology with buried pinned PD. The fabricated image sensor has a high sensitivity for 200–1100 nm light wave band, high robustness of sensitivity and dark current toward UV-light exposure and a wide DR of 97 dB. In this paper, the PD structures, the circuit, the operation sequence and the measurement results of this CMOS image sensor are discussed.

A prototype high-speed CMOS image sensor with 10,000,000 fps burst-frame rate and 10,000 fps continuous-frame rate

In this paper, a high-speed CMOS image sensor having a new architecture and a new operating principle has been developed. The image sensor achieves both the continuous capturing and the burst capturing by a single chip, and has low power consumption, low heat generation, high sensitivity and high S/N ratio. This image sensor consist of mainly four blocks, two dimensional pixel array of 4-transister CMOS active pixel, analog memory arrays connected with each pixel output line independently to the pixel array, scanning circuits and multiple number of output amplifiers. A prototype image sensor was fabricated using a 0.18μm 2-Poly 3-Metal CMOS technology with the die size of 5550 μmH x 4575 μmV, the pixel size of 48 μmH x 48 μmV, the number of pixels of 72H x 32V, the number of analog memories of 104 memories per pixel and the 6 parallel horizontal output circuits and output amplifiers. The aperture ratio is 35% and the conversion gain is 60 μV/e-(input referred). It has been confirmed that this image sensor achieves 10,000,000 fps during burst capturing mode and 10,000 fps during the continuous capturing mode through the image capture experiments of high speed phenomena such as rotating object and discharge phenomenon.

Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor

In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In this image sensor, the size of the photodiode (PD) is 30.0 μmH x 21.3 μmV in the 32.0 μmH x 32.0 μmV pixel. In the pixel, the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending from the edges of the semicircular regions. To generate an electric field greater than the average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. By using the PD structure, which includes the above mentioned n-layer shape and the PD dopant profile with the condition of three times n-type dopant implantation, we achieved to collect 96 % of the charges generated in the PD at the FD within 10 nsec. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed three key characteristics as follows; the image lag was below the measurement limit, the electron transit time in the PD was less than 10 nsec, and the entire PD region had equivalent sensitivity.

An ASIC implementation of phase correlation based on run-time reconfiguration technique

In this paper, we present an application-specific LSI that is designed using a run-time reconfiguration technique. The implemented algorithm is phase correlation. The calculation of phase correlation includes Fast Fourier Transform (FFT) followed by Inverse Fast Fourier Transform (IFFT). We have developed a dual-decimation butterfly module that can be self-reconfigured, at run-time, to be either decimation-in-time (DIT) or decimation-in-frequency (DIF). By sharing the common parts between the DIT and DIF butterfly modules, the dual-decimation butterfly module can reduce the logic size to about half. DIT-mode is used for FFT and DIF-mode is used for IFFT. No data reordering, such as natural-to-reverse or reverse-to-natural conversion, between FFT and IFFT is necessary. As a consequence, the amount of intermediate frame buffers and the number of memory accesses are significantly reduced.