Tomohiro Yoneda

Efficient Verification of Parallel Real–Time Systems

This paper presents an efficient model checking algorithm for one–safe time Petri nets and a timed temporal logic. The approach is based on the idea of (1) using only differences of timing variables to be able to construct a finite representation of the set of all reachable states and (2) further reducing the size of this representation by exploiting the concurrency in the net. This reduction of the state space is possible, because the considered linear–time temporal logic is stuttering invariant. The firings of transitions are only partially ordered by causality and a given formula; therefore the order of firings of independent transitions is irrelevant, and only one of several equivalent interleavings has to be generated for the evaluation of the given formula. In this paper the theory of timing verification with time Petri nets and temporal logic is presented, a concrete model checking algorithm is developed and proved to be correct, and some experimental results demonstrating the efficiency of the method are given.

Verification of analog/mixed-signal circuits using labeled hybrid petri nets

System on a chip design results in the integration of digital, analog, and mixed-signal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDL-AMS to LHPNs. To support formal verification, this paper presents an efficient zone-based state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixed-signal circuit examples

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.

Using partial orders for trace theoretic verification of asynchronous circuits

In this paper, we propose a method to generate the reduced state spaces in which the trace theoretic verification method of asynchronous circuits works correctly and efficiently. The state space reduction is based on the stubborn set method and similar ideas, but they have been extended so that the conformance checking works correctly in the reduced state space. Our state reduction algorithm also guarantees that a kind of simple liveness properties are correctly checked. Some experimental results show the efficiency of the proposed method.

Timed trace theoretic verification using partial order reduction

In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.

Improving Dependability and Performance of Fully Asynchronous On-chip Networks

Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems. In this paper, we propose fully asynchronous on-chip networks which have improved tolerance against stuck-at-faults, aging degradation faults and transient faults, as well as potential of high performance. We have developed a dependable routing algorithm to detour a faulty router or a faulty link based on local fault information. An adaptive routing algorithm based on local traffic load information is also used to achieve high performance. The proposed router circuits are based on the bundled-data method with MOUSETRAP-like transition signaling protocol, where programmable delay elements for the matched delays are used in order to tolerate static and dynamic delay variations. Duplicated control circuits for tolerating transient faults are also designed and evaluated. The LEDR (Level Encoded Dual Rail) encoding method is used in the link implementation to avoid the resetting phase overhead. The proposed on-chip networks are implemented using 130nm process technology for checking the correct functionality and evaluating performance.

BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets

This paper proposes using Zero-Suppressed BDDs for the CTL symbolic model checking of Petri nets. Since the state spaces of Petri nets are often very sparse, it is expected that ZBDDs represent such sparse state spaces more efficiently than BDDs. Further, we propose special BDD/ZBDD operations for Petri nets which accelerate the manipulations of Petri nets. The approaches to handling Petri nets based on BDDs and ZBDDs are compared with several example nets, and it is shown that ZBDDs are more suitable for the symbolic manipulation of Petri nets.

Verification of analog and mixed-signal circuits using timed hybrid petri nets

Embedded systems are composed of a heterogeneous collection of digital, analog, and mixed-signal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to model these circuits. In particular, this paper describes an efficient, approximate algorithm to find the reachable states of a THPN model. Using this state space, desired properties specified in ACTL are verified. To demonstrate these methodologies, a few hybrid automata benchmarks, a tunnel diode oscillator, and a phase-locked loop are modeled and analyzed using THPNs.

Synthesis of speed independent circuits based on decomposition

This work presents a decomposition method for speed-independent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the STG to include only transitions on the output of interest and its trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas (Nii-Utah timed asynchronous circuit synthesis system).

Automatic Derivation of Timing Constraints by Failure Analysis

This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure is obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.