Tomoki Ishii

Memory Aware Dynamic Load Balancing for Networks-on-Chip

Shared memory systems typically suffer from transmission load concentration on memories and routers. In this paper, we propose the method that resolves the load concentration problem and improves the memory access performance. This is achieved by distinguishing between the destination memories, balancing transmission load of memories and routers dynamically assuming shared memory system that has multiple memories. Hardware mounting evaluation reveal the proposed method improves the issue of transmission load concentration on shared memory system. In the 16 processing core, 4 memory system model, throughput was improved three times over conventional method, without significantly increasing the mounting footprint.