Tomoya Kodama

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

A single-chip MPEG-2 codec based on customizable media microprocessor

A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.

A highly parallelized H.265/HEVC real-time UHD software encoder

H.265/HEVC standard, promising up to twice the compression efficiency over H.264/AVC standard is suitable for encoding UHD videos and has garnered much attention since its inception. With increasing amount of devices supporting UHD, real-time H.265/HEVC encoder and decoder are needed to complete the UHD media ecosystem. In this paper, we present a highly parallelized HEVC software encoder suitable for broadcasting or network streaming applications. Real-time Main 10 profile encoding of 4K UHD videos at 60fps is achieved through an efficient parallel encoder platform comprising of CPUs interconnected by high speed network. The encoder core is optimized with data parallelism and GPU assisted motion estimation. Utilizing temporal parallelism of GOP and spatial parallelism of picture through slicing to encode, scalability and flexibility are achieved. Results show that our encoder system is about 15794 times faster than HEVC test model HM 11.0 and 13 times faster than ×265, an open source HEVC encoder.