Shinichiro Koto

A study on fast rate-distortion optimized coding mode decision for H.264

The H.264 video coding standard can achieve considerably higher coding efficiency than any other existing standards by deciding the best mode among many prediction modes and various sixes of prediction blocks. Although the coding efficiency is improved by using Lagrange optimization for the mode decision, computational complexity increases significantly at the encoder. In this paper, we propose the fast rate-distortion optimization method for the hierarchical and adaptive coding mode decision in order to reduce the number of candidates for the best coding mode.

Adaptive bi-predictive video coding using temporal extrapolation

In this paper, we propose a new multi-frame bi-predictive motion compensation method using a temporal linear extrapolation technique. Significant coding gain is obtained by the proposed method, especially for fading or dissolving scenes, which are among the most difficult scenes to compress by conventional coding standards. Moreover, stable improved coding efficiency is obtained, using block by block adaptation combined with multiframe averaging prediction. The number of reference frames for the proposed temporal prediction method is limited to two successive frames which are already coded. And therefore only addition, subtraction and shift operation are needed to generate the prediction signal of both extrapolation and averaging. As for encoding, automatic adaptation is performed without scene characteristics detection, such as fade-in, fade-out, and dissolve. Therefore, additional computational power for both encoder and decoder to use the proposed method is very small.

An H.264 full HD 60i double speed encoder IP supporting both MBAFF and Field-Pic structure

HD video sequences are widely used in todays multimedia systems and many of these are encoded with H.264 codec. However, it is still challenging to develop a high-performance H.264 encoder because the H.264 encoding process needs a large amount of computations and memory accesses. In this paper, a novel H.264 encoder is described. This encoder can encode video sequences of full HD 60i at double speed. Both MBAFF and Field-Pic structure are supported as coding tool for interlaced video sequences. The memory bandwidths are reduced by using a hierarchical motion estimation method and a pipeline configuration with consideration of MBAFF. The encoder is implemented with 1637K logic gates and 336.5KB on-chip SRAM in the 65nm CMOS technology.