Tomoyuki Ohshima

Effect of Growth Conditions on Electrical Properties of Si-Doped In0.52Al0.48As Grown by Metalorganic Vapor Phase Epitaxy

A systematic study of the electrical properties of Si-doped In0.52Al0.48As grown under various metalorganic vapor phase epitaxy (MOVPE) conditions such as V/III ratio and growth temperature is carried out. It is demonstrated that either high V/III ratios (≥64) or high growth temperatures (≥720°C) are necessary for obtaining good InAlAs electrical properties. For a small V/III ratio (=32) and low growth temperatures (≤700°C), a large discrepancy is found in Hall carrier concentration (nHall), ionized impurity concentration (NC – V), and Si concentration (NSi); NC – V>NSi>nHall; which can be explained by the dual formation of donor and acceptor deep levels. SIMS results suggest that carbon and oxygen impurities are not candidates for these deep levels, and other origins such as intrinsic defects, which are closely related to growth conditions, are applicable.

Gate Orientation Dependence of InGaAs/AlGaAs High Electron Mobility Transistors Formed by Wet Recess Etching

The gate orientation dependence of InGaAs/AlGaAs high electron mobility transistors (HEMTs) formed by the wet-chemical recess etching has been evaluated. The short channel effect strongly depends on the gate orientation and is significant in the order of [011], [001] and [011] oriented devices. Such orientation dependence results from a difference of the side-etching lengths, which are 0.01 µm, 0.03 µm and 0.06 µm for the [011], [001] and [011] oriented devices, respectively. The other characteristics of HEMTs such BVgd, gm and fT also depend on the gate orientation because of a difference of the recessed shape.

Schottky Characteristics of Subhalf-Micron Gate GaAs Metal-Semiconductor Field-Effect Transistor

This paper describes Schottky characteristics of the subhalf-micron W-Al gate GaAs metal-semiconductor field-effect transistor (MESFET), which is fabricated using the phase-shifting mask technology. We observed that Schottky characteristics depend on the gate length and gate direction especially in the subhalf-micron range. This phenomena is caused by the piezoelectric effect; however, the degree of the barrier height shift is small compared to that of the threshold voltage, and this can be explained by the depth profile of the induced charges under the gate of subhalf micron.

Schottky Characteristics of InAlAs Grown by Metal-Organic Chemical Vapor Deposition

Schottky characteristics of InAlAs grown by metal-organic chemical vapor deposition (MOCVD) have been evaluated. InAlAs Schottky characteristics are strongly affected by MOCVD growth temperature. The reverse current of InAlAs grown at 700°C is more than one order of magnitude larger than that at 750°C. From deep-level transient spectroscopy (DLTS) measurements, electron traps with activation energies of 0.45, 0.33 and 0.15 eV have been observed in InAlAs grown at 700°C. The results of C-V, Hall and secondary ion mass spectrometry (SIMS) measurements suggest that the trap is acceptor-type and seems to be related not to impurities but to intrinsic defects. The mechanism of the large reverse current in InAlAs grown at 700°C is believed to be due to the conduction through the trap.

Electron irradiation during Schottky gate metal evaporation and its effect on the stability of InGaAs/AlGaAs HEMTs

Abstract The threshold voltage of InGaAs/AlGaAs HEMTs with molybdenum Schottky gate were observed to shift after a high forward gate current test. Experimental results show that this phenomenon is characteristic of molybdenum Schottky gates on GaAs, and it is related to the deep traps near the interface between molybdenum (Mo) and GaAs or within the semiconductor to the depth of 1000A. Such deep traps were introduced because of the electron irradiation effect during the electron beam deposition of Mo on GaAs. Insertion of a Ti layer thicker than 100Abetween Mo and GaAs was found to be effective for suppressing the shift by the blocking effect for the electron irradiation.

0.1-µm-Gate Metamorphic High-Electron-Mobility Transistor on GaAs and Its Application to Source-Coupled Field-Effect Transistor Logic

The device performances of 0.1-µm-gate InxGa1-xAs/InyAl1-yAs metamorphic high-electron-mobility transistors (MM-HEMTs) on GaAs substrates, depending on the indium composition (XIn), have been investigated. By reducing the XIn, the gate-to-drain breakdown voltage (BVgd) of the MM-HEMT can be improved, while the transconductance (gm) and the current gain cut-off frequency (fT) decrease because of a reduction in electron mobility of the InxGa1-xAs channel. The balanced values of gm of 900 mS/mm, fT of 166 GHz and BVgd of 5.2 V for the MM-HEMT with XIn of 0.45 have been obtained. The propagation delay (tpd) of a source-coupled field-effect transistor logic (SCFL) inverter implemented by MM-HEMTs rapidly increases with decreasing XIn, due to the increase in series resistance of the Schottky diode in the source-follower circuit.

Shift in Threshold Voltage and Schottky Barrier Height of Molybdenum Gate Gallium Arsenide Field Effect Transistors after High Forward Gate Current Test

The threshold voltage and the Schottky barrier height of InGaAs/AlGaAs HEMTs or GaAs MESFETs with molybdenum Schottky gates were observed to shift after high forward gate current tests, and the shift was recovered by subsequent heat treatment. Experimental results show that this phenomenon is characteristic of molybdenum Schottky gates on GaAs, and it is related to the deep traps near the interface between molybdenum and GaAs or within the GaAs channel layer. Such deep traps were introduced due to the electron irradiation effect during the electron beam deposition of the molybdenum (Mo) on GaAs. Insertion of a thin Ti layer between Mo and GaAs was found to be effective for suppressing the shift.

Double-Recessed 0.1-µm-Gate InP HEMTs for 40 Gbit/s Optical Communication Systems

We have developed a double-recessed 0.1-µm-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are very important in terms of the device characteristics. In order to suppress the maximum electric field strength within the channel region and to reduce the source resistance (Rs), we have performed a device simulation and have obtained the optimum double-recessed gate structure. The DR-HEMT shows a good transconductance over drain conductance gain (gm/gd) of 26 and a high maximum oscillation frequency (fmax) of 351 GHz because of the improved gd with a small Rs. The propagation delay (tpd) of a source-coupled field effect transistor logic (SCFL) inverter implemented by DR-HEMTs is as fast as 5.8 ps/gate. We have applied the DR-HEMT technology to a static 1/2 frequency divider and obtained stable operation up to 43 GHz.

Evaluation of Effective Gate Length of Gallium Arsenide Metal-Semiconductor Field Effect Transistors.

To improve the performance of field-effect transistors (FETs), it is necessary to reduce the gate length. However the gate length, which affects the characteristics of FETs, is generally not the same as the metallurgical gate length, and is referred to as the effective gate length, which depends on the device structure. This paper describes a method of evaluating the effective gate length of GaAs MESFETs using I–V measurement under the bias condition, then discusses the relationship between the effective gate length and the structural parameters of the device, such as the distance between the gate metal and the n+ region, which is controlled by the sidewall thickness for n+ self-alignment ion implantation. From the results of a two-dimensional device simulation, it is observed that the effective gate length is related to the depletion layer extending around the gate electrode.

Application of phase-shifting mask technology to 0.17/spl mu/m-gate GaAs MESFET for ultra high speed IC's

Then W-Al was anisotropically etched by the electron cyclotron resonance (ECR) plasma using the Al pattern as a mask, where the difference between the resist spacing and the gate length was less than 0.02pm. A standard deviation of 0.17pm W-AI gate pattern obtained was as small as 0.019pm (9.5%) over a 3-inch wafer. After the gate formation, ion implantations of Si and C were performed to form n+-region and buried p-region which were self-aligned to the gate. This structure successfilly suppressed the short channel effect without sacrificing its high speed performance, namely, without increasing the parasitic capacitance. Fabricated 0.17pm-gate GaAs MESFETs have shown the averaged maximum transconductance of 622mmS/mm with the standard deviation of lOmmS/mm (1.6%) at the drain voltage of 1V. The uniformity of the threshold voltage was also good, and the standard deviation was 28mV over a 3-inch wafer. The DCFL (Direct-Coupled FET Logic) inverter implemented by this device has shown a propagation delay of 10.4pdgate with a power dissipation of 2.34mW/gate at the supply voltage of 2V as averaged values over a 3-inch wafer. These standard deviations were 0.28ps/gate (2.7%) and 0.053mW/gate (2.3%), respectively. As the highest value, we have observed the propagation delay of 7.6pdgate at a supply voltage of 1OV. Using this device we have fabricated 8: 1 multiplexer and 1 :8 demultiplexer, and obtained a stable operation at lOGb/s at a power dissipation as low as 1.5W and 2.0W, respectively. The demultiplexer has operated even at 14Gb/s, which is one of the best results ever reported. A yield of these ICs was over 50%, which was due to the high uniformity in the characteristics of the MESFETs. Finally, we have confirmed that the fabrication process of 0.17pm-gate GaAs MESFET based on the phase-shifting mask technology is promising for the ultra high speed digital IC application. Next, Al was evaporated and lifted-off