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Dive into the research topics where Masanori Tsunotani is active.

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Featured researches published by Masanori Tsunotani.


Japanese Journal of Applied Physics | 2000

Gate Orientation Dependence of InGaAs/AlGaAs High Electron Mobility Transistors Formed by Wet Recess Etching

Tomoyuki Ohshima; Masaaki Yoshida; Ryoji Shigemasa; Masanori Tsunotani; Tamotsu Kimura

The gate orientation dependence of InGaAs/AlGaAs high electron mobility transistors (HEMTs) formed by the wet-chemical recess etching has been evaluated. The short channel effect strongly depends on the gate orientation and is significant in the order of [011], [001] and [011] oriented devices. Such orientation dependence results from a difference of the side-etching lengths, which are 0.01 µm, 0.03 µm and 0.06 µm for the [011], [001] and [011] oriented devices, respectively. The other characteristics of HEMTs such BVgd, gm and fT also depend on the gate orientation because of a difference of the recessed shape.


Japanese Journal of Applied Physics | 1999

Schottky Characteristics of InAlAs Grown by Metal-Organic Chemical Vapor Deposition

Tomoyuki Ohshima; Hironobu Moriguchi; Ryoji Shigemasa; Shu Goto; Masanori Tsunotani; Tamotsu Kimura

Schottky characteristics of InAlAs grown by metal-organic chemical vapor deposition (MOCVD) have been evaluated. InAlAs Schottky characteristics are strongly affected by MOCVD growth temperature. The reverse current of InAlAs grown at 700°C is more than one order of magnitude larger than that at 750°C. From deep-level transient spectroscopy (DLTS) measurements, electron traps with activation energies of 0.45, 0.33 and 0.15 eV have been observed in InAlAs grown at 700°C. The results of C-V, Hall and secondary ion mass spectrometry (SIMS) measurements suggest that the trap is acceptor-type and seems to be related not to impurities but to intrinsic defects. The mechanism of the large reverse current in InAlAs grown at 700°C is believed to be due to the conduction through the trap.


Japanese Journal of Applied Physics | 2003

0.1-µm-Gate Metamorphic High-Electron-Mobility Transistor on GaAs and Its Application to Source-Coupled Field-Effect Transistor Logic

Tomoyuki Ohshima; Hironobu Moriguchi; Shinichi Hoshi; Masanori Itoh; Masanori Tsunotani; Toshihiko Ichioka

The device performances of 0.1-µm-gate InxGa1-xAs/InyAl1-yAs metamorphic high-electron-mobility transistors (MM-HEMTs) on GaAs substrates, depending on the indium composition (XIn), have been investigated. By reducing the XIn, the gate-to-drain breakdown voltage (BVgd) of the MM-HEMT can be improved, while the transconductance (gm) and the current gain cut-off frequency (fT) decrease because of a reduction in electron mobility of the InxGa1-xAs channel. The balanced values of gm of 900 mS/mm, fT of 166 GHz and BVgd of 5.2 V for the MM-HEMT with XIn of 0.45 have been obtained. The propagation delay (tpd) of a source-coupled field-effect transistor logic (SCFL) inverter implemented by MM-HEMTs rapidly increases with decreasing XIn, due to the increase in series resistance of the Schottky diode in the source-follower circuit.


Japanese Journal of Applied Physics | 2003

Double-Recessed 0.1-µm-Gate InP HEMTs for 40 Gbit/s Optical Communication Systems

Shinichi Hoshi; Hironobu Moriguchi; Masanori Itoh; Tomoyuki Ohshima; Masanori Tsunotani; Toshihiko Ichioka

We have developed a double-recessed 0.1-µm-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are very important in terms of the device characteristics. In order to suppress the maximum electric field strength within the channel region and to reduce the source resistance (Rs), we have performed a device simulation and have obtained the optimum double-recessed gate structure. The DR-HEMT shows a good transconductance over drain conductance gain (gm/gd) of 26 and a high maximum oscillation frequency (fmax) of 351 GHz because of the improved gd with a small Rs. The propagation delay (tpd) of a source-coupled field effect transistor logic (SCFL) inverter implemented by DR-HEMTs is as fast as 5.8 ps/gate. We have applied the DR-HEMT technology to a static 1/2 frequency divider and obtained stable operation up to 43 GHz.


Solid-state Electronics | 1999

Improvement of 0.1 μm-gate InGaAs/AlGaAs HEMT performance by suppression of electro-chemical etching in deionized water

Tomoyuki Ohshima; Ryoji Shigemasa; Masakatsu Sato; Masanori Tsunotani; Tamotsu Kimura


Archive | 1987

Method of manufacturing schottky gate field transistor by ion implantation method

Tadashi Saito; Hiroshi Nakamura; Masanori Tsunotani


The Japan Society of Applied Physics | 1997

Development of the High Aspect-Ratio Y-Shaped Gate Process for HEMT

Ryoji Shigemasa; Yoshiki Nitta; Tomoyuki Ohshima; Masanori Tsunotani; Tamotsu Kimura


The Japan Society of Applied Physics | 1984

The Effect of Substrate Purity on Short-Channel Effects of GaAs MESFET's

Hiroshi Nakamura; Masanori Tsunotani; Yoshiaki Sano; Toshio Nonaka; Toshimasa Ishida; Katsuzo Kaminishi


The Japan Society of Applied Physics | 2002

Double-recessed 0.1-μm-gate InP HEMTs for 40-Gb/s Optical Communication Systems

Shinichi Hoshi; Hironobu Moriguchi; Masanori Itoh; Tomoyuki Ohshima; Isamu Matsuyama; Masanori Tsunotani; Toshihiko Ichioka


Archive | 2002

GaAs pHEMT Technology for Optical Communication System

Tamotsu Kimura; Tomoyuki Ohshima; Masanori Tsunotani; Toshihiko Ichioka; Shohei Seki

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