Tony DiBiase

Process window impact of progressive mask defects, its inspection and disposition techniques (go / no-go criteria) via a lithographic detector

Progressive mask defect problem is an industry wide mask reliability issue. During the start of this problem when the defects on masks are just forming and are still non-critical, it is possible to continue to run such a problem mask in production with relatively low risk of yield impact. But when the defects approach more critical state, a decision needs to be made whether to pull the mask out of production to send for clean (repair). As this problem increases on the high-end masks running DUV lithography where masks are expensive, it is in the interest of the fab to sustain these problem masks in production as long as possible and take these out of production only when absolutely necessary; i.e., when the defects have reached such a critical condition on these masks that it will impact the process window. During the course of this technical work, investigation has been done towards understanding the impact of such small progressive defects on process window. It was seen that a small growing defect may not print at the best focus exposure condition, but it can still influence the process window and can shrink it significantly. With the help of a high-resolution direct reticle inspection, early detection of these defects is possible, but fabs are still searching for a way to disposition (make a go / no-go decision) on these defective masks. But it is not an easy task as the impact of these defects will depend on not only their size, but also on their transmission and MEEF. A lithographic detector has been evaluated to see if this can predict the criticality of such progressive mask defects.

Full spectral analysis of line width roughness

Various approaches can be used to quantify line width roughness (LWR). One of the most commonly used estimators of LWR is the standard deviation. However, this approach is incomplete and ignores a substantial amount of information. We propose here a full spectral analysis to investigate and monitor LWR. A variety of estimators, such as standard deviation, peak-to-valley, average, correlation length and Fourier analysis have been implemented on-line on CDSEM. The algorithms were successfully tested against e-beam written LWR patterns, both deterministic and random. This approach allows a fully automated investigation of LWR. This methodology was used to monitor LWR over a long period of time, benchmark new resists and to investigate the effect of LWR on device performance and yield.

Spectral analysis of line width roughness and its application to immersion lithography

Various approaches can be used to quantify line width rough- ness LWR. One of the most commonly used estimators of LWR is standard deviation . However, a substantial amount of information is ignored if only is measured. We use an automated approach to inves- tigate LWR, where standard deviation, correlation length, and power spectrum are measured online on critical dimension scanning electron microscopes. This methodology is used to monitor LWR, investigate the effect of LWR on critical dimension precision, and to benchmark new resists for immersion lithography. Our results indicate that online LWR metrology is a critical tool in a variety of applications, including but not restricted to process control.

An Investigation of EUV Lithography Defectivity

We have used ASMLs full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks. The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also integrated into a standard process flow where the other layers were patterned using more conventional 193-nm lithography techniques. This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the 28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find good correlations between reticle level defects and the resulting wafer exposure defects.

Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.

A methodology for the characterization of topography induced immersion bubble defects

A key issue regarding the introduction of 193nm immersion lithography into production is immersion specific defects. One of these new defect types is the formation of air bubbles in the immersion fluid near or on the resist surface, which can then cause significant local dose variations. One possible mechanism for inducing bubble formation is the introduction of surface topography, such as seen on a typical product wafer, which could then disrupt the immersion fluid flow and entrain air. This brings up the question of what, if any, types of topography we need to be worried about and how do we test all the possible variants that will exist on product wafers. To help address this issue we have created a special topography reticle and wafer set and used them for exposures on a prototype immersion scanner. The wafer set was generated using a first level reticle designed to have an extremely wide range of topography types in a modular and systematically varying format. The wafer fabrication included skews of the trench depths, variation of the surface contact angle by using different topcoats, and optimization of the process flow to enable high contrast defect inspections. The second level reticle used for the immersion exposures was designed to cover the entire topography wafer with dose sensitive grating structures to detect any dose modulation caused by bubbles. In this paper we present the design of these reticles and wafers and the results of the first immersion exposures. Flat, unpatterned wafers were also exposed on the immersion tool in order to provide a basis for comparison. A KLA 2351 inspection tool was used to inspect all the wafers for defects. The initial results of these tests did not show a strong interaction of bubbles with topography.

Building 1x NIL templates: challenges and requirements

Recent interest and inclusion to the ITRS roadmap for the investigation of NIL (Nano Imprint Lithography) has brought back to life 1X mask making. Not only does NIL require 1X pattering, it also requires physical contact with the patterning media, which, for obvious reasons, raises defectivity concerns. NIL is capable of reproducing features in the 50-10nm range, and possibly below, creating extensive manufacturing challenges for NIL tooling. KLA-Tencor has partnered with Molecular Imprints Inc. of Austin, Texas to study the eventual implementation and commercialization of NIL, especially as it pertains to the IC segment of the market. Photronics Labs Inc. is also involved in the NIL effort by developing and understanding the issues required for successfully producing commercially available tooling for this new lithography technique. Much of this work supported by NIST project #00-00-5853.