Sumanth Kini

An Investigation of EUV Lithography Defectivity

We have used ASMLs full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks. The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also integrated into a standard process flow where the other layers were patterned using more conventional 193-nm lithography techniques. This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the 28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find good correlations between reticle level defects and the resulting wafer exposure defects.

Process Window Centering for 22 nm lithography

Process window centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between focus exposure matrix, where centering is based only on critical dimension measurements of a few specific structures and process window qualification which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBMs Albany, NY, and East Fishkill, NY, development facilities using KLA-Tencors 28xx brightfield defect inspection system.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.

Line end voids defectivity improvement on 64 pitch Cu wire interconnects of 14 nm technology

Semiconductor manufacturing of 14 nm devices has presented numerous engineering and manufacturing challenges from newly introduced FinFETs in the FEOL to double patterned trenches and self-aligned vias in the BEOL. Voids are a common defect found in the metal interconnects of the BEOL of any technology, more generally occurring in the thinner pitch size copper metal wires. Voids manifest themselves in many forms like line voids, island voids, seam voids, line end voids, point voids, etc., depending on the location, orientation and mechanism of occurrence. Small process marginality between the CuMn seed deposition and Cu plating processes is the primary source of voids in Cu interconnects. In this paper, we will discuss in-line LEV inspection solutions as well as the causes and methods to improve line end voids (LEV) in 64 nm pitch Cu-wire interconnects for the 14nm technology node.

Assessing EUV mask defectivity

This paper assesses the readiness of EUV masks for pilot line production. The printability of well characterized reticle defects, with particular emphasis on those reticle defects that cause electrical errors on wafer test chips, is investigated. The reticles are equipped with test marks that are inspected in a die-to-die mode (using DUV inspection tool) and reviewed (using a SEM tool), and which also comprise electrically testable patterns. The reticles have three modules comprising features with 32 nm ground rules in 104 nm pitch, 22 nm ground rules with 80 nm pitch, and 16 nm ground rules with 56 nm pitch (on the wafer scale). In order to determine whether specific defects originate from the substrate, the multilayer film, the absorber stack, or from the patterning process, the reticles were inspected after each fabrication step. Following fabrication, the reticles were used to print wafers on a 0.25 NA full-field ASML EUV exposure tool. The printed wafers were inspected with state of the art bright-field and Deep UV inspection tools. It is observed that the printability of EUV mask defects down to a pitch of 56 nm shows a trend of increased printability as the pitch of the printed pattern gets smaller - a well established trend at larger pitches of 80 nm and 104 nm, respectively. The sensitivity of state-of-the-art reticle inspection tools is greatly improved over that of the previous generation of tools. There appears to be no apparent decline in the sensitivity of these state-of-the-art reticle inspection tools for higher density (smaller) patterns on the mask, even down to 56nm pitch (1x). Preliminary results indicate that a blank defect density of the order of 0.25 defects/cm2 can support very early learning on EUV pilot line production at the 16nm node.

Novel methods for SPC defect monitoring: Normalizable diversity sampling: Defect inspection

The key to robust SPC control is the inline signals provided by metrology tools (e.g. CD-SEM, Overlay, film thickness measurement) and defect inspection tools (e.g. Surfscan, Broadband Plasma (BBP), Laser Scanning). Wafer defect inspection tools like Broadband Plasma find anomalies and provide defect coordinates to report their locations. Defects reported by the inspection tools are then sampled, or in other words, a sub-set of those defects are chosen for Scanning Electron Beam (SEM) Review. Classification of the defect type is provided using SEM. Due to SEM review throughput limitations, not every defect reported by inspection can be sampled for review. Therefore, the theoretical ideal sampling technique would generate an accurate representation of the true defect population on a wafer solely based on a limited review sample. The paper discusses the methodology for selecting such a review sample, termed diversity sampling. This scheme samples defects based on properties (location on wafer / die, design location, optical characteristics) instead of sampling solely based on defect location. Compared to random sampling, this technique demonstrates reduced error between the normalized defect density reported and the true defect density actually present on the wafer.

Non-traditional inspection strategy for inline monitoring in excursion scenarios: Defect inspection

Different tool platforms are used in conjunction for patterned wafer inspection like 9xxx & 29xx provided by KLA Tencor. Depending on the sensitivity & throughput requirements, a chip fabrication plant mixes and matches the inline inspection strategies to ensure early detection of defects on the chip, which could cause yield loss or reliability problems. This paper discusses the use of a novel concept of high sensitivity & high throughput inspection strategy using the 29xx tool. This is achieved by using a unique combination of Broad-Band light with Dark Field Apertures. This application can be used to monitor and screen a large number of wafers affected by out of control situations. A use-case is also discussed where optically strong defect locations uniquely seen on 29xx tool were found to be invisible after SEM review. After analyzing defects using see-through imaging on Scanning Electron Microscope (SEM), along with Transmission Electron Microscope (TEM) of the defect locations, those defects were confirmed to be buried defects inside the current layer. Due to low sampling on inspection tools, it was difficult to determine the quantity of wafers affected by the issue. By using high throughput (TPT) 29xx features, a methodology to screen out a high volume of wafers at high throughput was implemented & used to monitor the variability in the process and identify wafers at risk. This methodology enabled inspection of ~15 wafers per hour. The same methodology was subsequently successfully implemented to verify/monitor multiple excursion scenarios at different process steps.

Inspection of high-aspect ratio layers at sub 20nm node

High aspect ratio defects are more critical at sub 20nm design rule. The impact of these defects in the FEOL module is very critical as it leads to gate leakage which directly translates to yield loss at sub 20nm devices. Image 1a) and 1b) shown below is one such example of a high aspect ratio protrusion seen during the HiK stack for gate last process on a sub 20nm device. False and nuisance defects detected by optical inspection tools, degrade the inspection sensitivity of the tool to real and critical defects[1]. The intention of this paper would be to target two critical FEOL layers post Litho and post etch to detect these critical yield impacting defects using KLA-Tencor 2905 broadband brightfield inspection system for early development learning. In this paper we will discuss the DOE on all the different inspection points to intentionally generate these defects and summarize all the findings.

Optimization of pitch-split double patterning photoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.