Torkel Arnborg

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

The future of cellular radio ICs lies in the integration of an ever-increasing number of bands and channel bandwidths. Figure 21.2.1 shows the block diagram of our transceiver, together with the associated discrete front-end components. The transceiver supports 4 EDGE bands and 9 WCDMA bands (I-VI and VIII-X), while the radio can be configured to simultaneously support the 4 EDGE bands and up to 5 WCDMA bands: 3 high bands (HB) and 2 low bands (LB). The RX is a SAW-less homodyne composed of a main RX and a diversity RX. To reduce package complexity with so many bands, we chose to minimize the number of ports by using single-ended RF interfaces for both RX and TX. This saves several package pins, but requires careful attention to grounding. The main RX has 8 LNA ports and the diversity RX has 5, with some LNAs supporting multiple bands. On the TX side, 2 ports are used for all EDGE bands and 4 for the WCDMA bands.

A fast 3D modeling approach to electrical parameters extraction of bonding wires for RF circuits

Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF applications. An approach to fast three-dimensional (3D) modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the frequency response of bonding wires. To verify simulation accuracy, test structures have been made and measured. Excellent agreement between simulated and measured data is achieved for frequencies up to 10 GHz. The model is well suited for the design and analysis of circuits for cellular phone communication (i.e., order 2 GHz) and future wireless communication (i.e., order 5 GHz).

Device simulation for RF applications

The rapid growth of wireless systems at radio frequencies (RF) is driving the need for improved analog circuit and device analysis at gigaHertz frequencies. This includes: low noise front ends, linear amplifiers, mixers, and power amplifiers. Moreover, the parasitic effects of capacitance and inductance, both on- and off-chip, require careful extraction and characterization in support of predictive modeling. While time-domain techniques work well for digital systems, often the spectral and dynamic range requirements for communications systems necessitate accurate analysis of harmonic content with frequency differences of a thousandfold or more. This paper demonstrates the applicability and unique strengths of device-level harmonic balance (HB) in the simulation and physical modeling of RF circuits.

Implanted collector profile optimization in a SiGe HBT process

Abstract Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f T to be increased without degrading the collector emitter breakdown voltage BV CEO . The fabricated devices demonstrate a highest f T of 60 GHz. Depending on the collector profile BV CEO values between 1.5 and 2 V were obtained.

A novel approach to 3-D modeling of packaged RF power transistors

Packaged radio frequency (RF) power transistors with internal matching networks for use at 1.8-2 GHz in cellular base stations have been modeled using three-dimensional (3-D) electromagnetic-field simulators and SPICE. A method for extracting the actual internal 3-D geometries applying scanning electron microscope micrographs and software running in Java was developed. The results show good correlation between measured and simulated data in the 0.1-6 GHz interval studied. The importance of the mutual coupling and capacitance contributions from the package was demonstrated for different frequency domains. The described approach provides an interesting and promising method for modeling the interior parts of RF power transistors or other complex package structures, where geometry and coupling play a far greater role than for integrated-circuit packages.

Characterization of RF power BJT and improvement of thermal stability with nonlinear base ballasting

A novel base ballasting scheme for interdigitated power RF bipolar transistors has demonstrated improved performance and thermal stability. The nonlinear ballast resistor in series with each base finger is implemented using a depletion-mode FET, which requires only minor modification in the fabrication process. Mixed-mode simulation, instead of analytical equations, is used for more accurate device characterization.

Compact very high voltage CMOS compatible bipolar silicon-on-insulator transistor

A new type of bipolar transistor on SOI material (Silicon-On-Insulator) without buried layer has been fabricated in a standard 1.3 /spl mu/m CMOS process with only few additional mask steps. It is shown by measurements that the I-V characteristics of both pnp and npn transistors are comparable to conventional vertical transistors with buried layer. The voltage capability of devices made in thin silicon layers is substantially high and strongly affected by substrate bias effects. The transistors designed in a few micrometer thick silicon layer have a breakdown voltage BVceo of about 200 volts and also a remarkably high Early voltage, with highest measured value of 4000 V. The transistor will have a strong impact on the feasibility to realise mixed analogue and digital signal circuits with high and low voltage functions on the same chip.

Wideband inductorless LNA employing simultaneous 2 nd and 3 rd order distortion cancellation

This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.

3D characterization of RF power transistors

3D electromagnetic simulations and SPICE were used to model the influence of wire geometry, internal matching networks and package on the characteristics of high-power RF transistors for cellular base stations. A method for extracting the actual internal 3D geometries by applying SEM micrographs and Java software was developed. Measured transistor data was correlated with simulated data, and the importance of the contributing elements and the mutual coupling of the bond wires was demonstrated.

Improved performance and thermal stability of interdigitated power RF bipolar transistors with nonlinear base ballasting

A novel base ballasting scheme for interdigitated power RF bipolar transistors has demonstrated improved performance and thermal stability. The nonlinear ballast resistor in series with each base finger is implemented by depletion-mode FET, which requires only minor modification in the fabrication process. Mixed mode simulation, instead of analytical equations, is used for more universal device analyses.