Andrej Litwin

Impact of pad and gate parasitics on small-signal and noise modeling of 0.35 /spl mu/m gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters.

Small-signal substrate resistance effect in RF CMOS identified through device simulations

An anomalous dip in the measured s/sub 22/ characteristic, as well as a decrease in the output resistance, of MOS devices for rf applications was found to be a pure ac effect caused by the small-signal substrate transconductance. The study of the ac characteristics of multifinger transistors in rf applications with a high-resistivity substrate also puts a question mark on the possibility of achieving fully scalable models, considering the observed ac substrate effect.

Lateral current-constriction in vertical devices using openings in buried lattices of metallic discs

Vertical channels in semi-insulating GaAs were realized by epitaxial overgrowth over lattices of W discs, including n×n vacant positions. The Schottky depletion around the metallic inclusions is responsible for the semi-insulating behavior, and, thus, conducting channels may be created in designed openings in the lattice. By measuring the current transport in structures with varying sizes of the channels, we demonstrate that the current is actually restricted to floating through the vacant positions. We further buried the metal discs, including openings, 60 nm above a resonant tunneling structure, and measured a negative differential resistance, with peak currents scaling with the opening area. These experiments demonstrate the effective combination of semiconductor heterostructures and embedded metal features for submicron, vertical injection into a heterostructure device.

Planarization of epitaxial GaAs overgrowth over tungsten wires

We report on thin GaAs epitaxial overgrowth over tungsten wires. The aim of the study is to overgrow the grating without the formation of voids above the tungsten wires and to investigate the planarization of the growth front over the grating. It is established that the most important factors for rapid planarization of the overgrowth for given epitaxial conditions are the crystallographic orientation of the grating, the grating period, and the ratio of the growth rates for the different facets formed in the growth front. For a 300 nm period grating and a metal width of 100 nm, a planarized growth front is demonstrated after 200 nm of growth.

MOVPE overgrowth of metallic features for realisation of 3D metal–semiconductor quantum devices

Abstract We have studied the growth conditions for epitaxial overgrowth over metallic features using low-pressure metalorganic vapour phase epitaxy. The aim of this study is to optimise the growth conditions and to establish a processing sequence for the realisation of 3D metal–semiconductor quantum devices. First, we investigate the effect of the metal pattern (orientation and shape) on the resulting growth behaviour under fixed epitaxial conditions. Then we use the same pattern and vary the growth temperature in order to optimise the lateral growth above the metal. An excellent crystalline quality of the overgrown material is thereafter demonstrated using transmission electron microscopy. Finally, it is demonstrated how these structures may be used in two types of quantum devices, namely as storage elements in a semi-insulating layer and as an active part in a resonant tunnelling transistor.

Lateral confinement in a resonant tunneling transistor with a buried metallic gate

We have fabricated a resonant tunneling transistor by epitaxial overgrowth over a tungsten grating placed 30 nm above a GaAs/GaInP semiconductor, double barrier, resonant tunneling heterostructure. The Schottky depletion around the buried metal contacts controls the current to a vertical transistor channel. The lateral extension of this channel is defined by a square opening in the grating with a side length of 1.4 μm, which corresponds to a sub-μm electrical width. The transport properties at 20 K show a fine structure in the resonant tunneling characteristics, and it is affected by the gate bias. These effects are discussed in terms of lateral quantum confinement in the transistor channel defined.

Controlled Carrier Depletion around Nano-Scale Metal Discs Embedded in GaAs.

Matrices of uncontacted, nano-scale, tungsten discs, embedded in GaAs by epitaxial overgrowth, have been characterised electrically. By varying the spacing between the discs, it is demonstrated that when the disc separation is smaller than 300 nm (for a doping level of 1016 cm-3), the conductance drops by seven orders of magnitude and the material becomes semi-insulating. The presence of the metal-induced barrier is deduced from the temperature dependence of the current transport. These results are discussed in terms of overlapping Schottky depletion regions around the discs.

90-nm CMOS for microwave power applications

We report, for the first time, the experimental evaluation of a very short channel 90-nm CMOS transistor under RF over-voltage conditions. At 9 GHz and 1.5 V supply a 40 /spl mu/m gate width device is able to deliver 370 mW/mm output power with a PAE of 42% and a transducer power gain of 15 dB. Measurement results at 3 and 6 GHz is also presented. The transistor does not show any degradation in either dc or RF performance after prolonged operation at 1 and 6 dB compression. Simulation show, that the peak voltage, V/sub ds/ at this condition is 3.0 V, while the maximum allowed dc supply voltage is limited by the design rules to 1.2 V. We show for the first time that nanometer-scale CMOS can be used for microwave power applications with severe RF over-voltage conditions without any observable degradation.

Operation of a ballistic heterojunction permeable base transistor

A ballistic heterojunction permeable base transistor (HPBT) is proposed and an analytical and numerical analysis of the device is performed. The new feature of the device structure is an AlGaAs hetero-emitter for injection of hot electrons into a 150-nm-thick GaAs base layer. A tungsten grating is embedded in the base layer and the Schottky depletion around the metal wires controls the vertical current. In this investigation, it is established that the high velocity of the hot electrons will prevent charge accumulation in the base layer. Thereby the dependence of the doping on the transconductance is lower than for the permeable base transistor. The HPBT is expected to have a unity-current gain cut-off frequency above 300 GHz.

GaAs metalorganic vapour phase epitaxial overgrowth over nm-sized tungsten wires

Epitaxial overgrowth of GaAs over nanometer-sized tungsten patterns is studied experimentally. The relationships between the quality of the overgrowth and geometrical parameters, such as crystallographic orientation, metal width, metal thickness, and grating period, are investigated. The overgrown structures are characterized using a scanning electron microscope at top surfaces and at cleaved edges, and by I-V measurements of Schottky diodes formed between the metal grid and the overgrown GaAs. It is established that it is possible to obtain a high-quality overgrowth layer with a completely planarized growth front within 200 nm of growth.