Toshihiko Nagano

Characteristics of interface-engineered Josephson junctions using a YbBa2Cu3Oy counterelectrode layer

We have fabricated interface-engineered junctions with YbBa2Cu3Oy as the counterelectrode. The junctions fabricated on YBa2Cu3Oy base electrodes exhibited excellent Josephson characteristics with the 1σ-spread in Ic as low as 5.4% for 16 junctions with an average Ic of around 1 mA. We also confirmed that the 1σ in Ic correlates with the surface morphology of the base-electrode layer, indicating that further improvements in 1σ would be possible by advancing the thin-film growth technology.

RF-MEMS Tunable Capacitor With 3 V Operation Using Folded Beam Piezoelectric Bimorph Actuator

Tunable capacitors with high tuning range and high Q-factors are indispensable for realizing reconfigurable radio-frequency (RF) circuits for multiband/multimode next-generation mobile wireless communication terminals. A novel RF microelectromechanical systems tunable capacitor having a piezoelectric bimorph actuator has been developed using a complementary metal-oxide-semiconductor compatible surface micromachining process. Folded beam piezoelectric actuators were introduced to cancel curling of the actuator beam due to residual stress. The continuous wide tuning ratio of three was realized at an operation voltage of less than 3 V for the first time

A novel multilayer process for HTS SFQ circuit

We have developed a novel multilayer process for HTS-SFQ circuits adopting a NBCO groundplane and tin-oxide isolation layers, and fabricated an HTS-SFQ ring oscillator circuit including 21 Josephson junctions. The junctions on the buried groundplane exhibited excellent Josephson characteristics with a magnetic modulation of I/sub c/ exceeding 90%, and an I/sub c/R/sub n/ product of 0.75 mV at 30 K. The sheet inductance of the wiring layer at 30 K was evaluated to be 1.1 pH for the counter-electrode layer, and 1.3 pH for the base-electrode layer. We confirmed the correct operation of the 10-stage ring oscillator at 20-30 K. The maximum dc output voltage of the ring oscillator was 0.06 mV at 30 K and 0.12 mV at 20 K, indicating the signal delay per stage of 3.4 ps and 1.8 ps, respectively.

a-axis oriented YBa2Cu3Oy thin films grown on novel buffer layers

Abstract Preferable growth conditions for preparing a -axis oriented YBa 2 Cu 3 O y (YBCO) and PrBa 2 Cu 3 O y (PBCO) thin films on SrTiO 3 substrates were investigated. The structural analysis of thin films deposited at various substrate temperatures and growth rates revealed that cubic structure films with high crystallinity were grown at relatively low substrate temperatures in the YBaCuO system and at a high deposition rate in the PrBaCuO system, respectively. Although the a axis orientation growth of YBCO was found to be enhanced on the cubic-YBCO film with excellent lattice matching with YBCO, a large density of segregated particles was observed both in the cubic-YBCO films and the YBCO films grown on them. The surface morphology of a -axis oriented YBCO thin films was significantly improved by utilizing a cubic-YBCO/cubic-PBCO bilayer buffer. The surface roughness of the 250 nm thick a -axis oriented YBCO thin film grown on the bilayer buffer was confirmed to be less than 2.5 nm and the T c onset reached 90 K.

Analysis of I/sub c/ spreads in interface engineered junctions

We have investigated the electrical properties of interface engineered junctions fabricated under various process conditions to clarify the possible origin of the spreads in I/sub c/ and R/sub n/ values. We found that in most cases, the I/sub c/R/sub n/, values of junctions on a wafer scaled with the square root of I/sub c/. The distribution of both the junction I/sub c/ and R/sub n/ were expressed well by the log-normal distribution function with their /spl sigma/ values being different by a factor of two. These results indicate that Cooper pairs and quasiparticles in the junctions transfer through different transport channels, i.e., direct tunneling for the former and resonant tunneling for the latter, and that a variation in the tunnel barrier thickness among junctions dominates the spreads in the I/sub c/ and R/sub n/ values. In contrast, we could not observe a universal scaling relation between I/sub c/R/sub n/, and I/sub c/ among junctions processed under different conditions. This indicates that the I/sub c/ variation due to process conditions originates from something other than a simple barrier-thickness variation.

Piezoelectric RF MEMS tunable capacitor with 3V operation using CMOS compatible materials and process

A RF MEMS tunable capacitor having a piezoelectric bimorph actuator was developed using a CMOS compatible surface micromachining process. Folded beam piezoelectric actuators were introduced to cancel carling. Its continuous wide tuning ratio of 3 was realized at less than 3 V operations for the first time

Piezoelectric MEMS Variable Capacitor for a UHF Band Tunable Built-in Antenna

A UHF band tunable built-in antenna is realized using piezoelectric MEMS variable capacitors. The variable capacitor, which is driven by a piezoelectric actuator, has a tuning ratio of 11 with control voltage ranging from 0 to 8 V and quality factor of more than 37 at 650 MHz. The built-in antenna, which is an inverted-F antenna, is mounted at the top of an upper PCB board of a clamshell mobile phone, and the antenna element has a meander shape for a built-in structure. In the tunable built-in antenna, the variable capacitor is connected to one point of the meander structure of the built-in antenna. The antenna covers a frequency from 510 to 800 MHz with an efficiency of more than -3.5 dB, or the relative bandwidth of 44% by changing the value of the variable capacitor.

Design and fabrication of a voltage divider utilizing high-T/sub c/ ramp-edge Josephson junctions with a ground plane

Circuit operation of a voltage divider utilizing YBa/sub 2/Cu/sub 3/O/sub x//Co-doped PrBa/sub 2/Cu/sub 3/O/sub y//YBa/sub 2/Cu/sub 3/O/sub x/ ramp-edge Josephson junctions with a ground plane was demonstrated for the voltage region of 0-400 /spl mu/V at 12.5 K, where the maximum voltage corresponds to /spl sim/200 GHz internal Josephson oscillation. This voltage was around the critical current-normal resistance (I/sub c/R/sub n/) product of 420 /spl mu/V. In the design of the voltage divider, a transmission line model was adopted for an inductance loop because of the large dielectric constant of the insulation layer interposed between the ground plane and the wiring serving as a loop inductance. In the fabrication of the circuit, a SrTiO/sub 3//Co-doped PrBa/sub 2/Cu/sub 3/O/sub y//SrTiO/sub 3/ multilayer insulation and four-directional ramp-edge junction process using a photoresist reflow technique were adopted.

Current transport in interface-engineered high-Tc Josephson junctions

Abstract The mechanisms of current transport in interface-engineered junctions (IEJs) were investigated based on more than 400 junctions fabricated under various process conditions. We confirmed that the IcRn values of IEJs scaled with the square root of the Josephson critical current density (Jc) universally, as long as the junctions had a low critical current density of less than 1×104 A/cm2 at 4.2 K. These low-Jc junctions exhibited dI/dV profiles peculiar to inelastic tunneling via two or less localized states with some remnant of a smeared superconducting gap. In contrast, we could not observe a universal scaling relation between IcRn and Jc among higher-Jc junctions. The maximum IcRn values of IEJs having Jc ranging from 104 to 106 A/cm2 were limited to 2–3 mV at 4.2 K. The dI/dV profiles of these high-Jc junctions differed considerably from those of low-Jc junctions, and were characterized by a highly smeared-out superconducting gap with a reproducible sub-gap structure. The differential conductance at high bias voltages increased slightly with decreasing temperature. These results indicate that a simple tunneling picture is inadequate to describe IEJs with high-Jc values.

Optimization of Deposition Process and Microscopic Characterization of Highly Oriented Aluminum Nitride Thin Films for Bimorph Structures of Piezoelectric Tunable Capacitors

Film deposition with RF sputtering to control residual stress in aluminum nitride (AlN) thin films has been investigated to fabricate the bimorph actuator for a piezoelectric tunable capacitor with low-voltage operation. The effects of conditions in sputtering and surface cleaning were studied both to obtain a preferable film orientation for piezoelectric actuation and to suppress structural deformation of the cantilever due to the residual stress in films. Microscopic analysis revealed that (0001)-oriented AlN and (111)-oriented Al films were epitaxially grown at each interface in the bimorph structure. The current–voltage (I–V) measurements showed a leakage current of less than 5 ×10-5 A m-2 in 500-nm thick AlN films up to 30 V. The effect of optimization of process parameters was demonstrated by the capacitance–voltage (C–V) characteristics of the folded-beam tunable capacitor, in which the suppression of residual stress in piezoelectric layers was shown to be effective to obtain low-voltage operation.