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Dive into the research topics where Hiroshi Katsuno is active.

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Featured researches published by Hiroshi Katsuno.


Applied Physics Letters | 2001

Characteristics of interface-engineered Josephson junctions using a YbBa2Cu3Oy counterelectrode layer

Hiroshi Katsuno; Soichi Inoue; Toshihiko Nagano; Jiro Yoshida

We have fabricated interface-engineered junctions with YbBa2Cu3Oy as the counterelectrode. The junctions fabricated on YBa2Cu3Oy base electrodes exhibited excellent Josephson characteristics with the 1σ-spread in Ic as low as 5.4% for 16 junctions with an average Ic of around 1 mA. We also confirmed that the 1σ in Ic correlates with the surface morphology of the base-electrode layer, indicating that further improvements in 1σ would be possible by advancing the thin-film growth technology.


IEEE Transactions on Applied Superconductivity | 2003

A novel multilayer process for HTS SFQ circuit

Hiroshi Katsuno; Soichi Inoue; Toshihiko Nagano; Jiro Yoshida

We have developed a novel multilayer process for HTS-SFQ circuits adopting a NBCO groundplane and tin-oxide isolation layers, and fabricated an HTS-SFQ ring oscillator circuit including 21 Josephson junctions. The junctions on the buried groundplane exhibited excellent Josephson characteristics with a magnetic modulation of I/sub c/ exceeding 90%, and an I/sub c/R/sub n/ product of 0.75 mV at 30 K. The sheet inductance of the wiring layer at 30 K was evaluated to be 1.1 pH for the counter-electrode layer, and 1.3 pH for the base-electrode layer. We confirmed the correct operation of the 10-stage ring oscillator at 20-30 K. The maximum dc output voltage of the ring oscillator was 0.06 mV at 30 K and 0.12 mV at 20 K, indicating the signal delay per stage of 3.4 ps and 1.8 ps, respectively.


Physica C-superconductivity and Its Applications | 2002

Current transport in interface-engineered high-Tc Josephson junctions

Jiro Yoshida; Hiroshi Katsuno; Soichi Inoue; Toshihiko Nagano

Abstract The mechanisms of current transport in interface-engineered junctions (IEJs) were investigated based on more than 400 junctions fabricated under various process conditions. We confirmed that the IcRn values of IEJs scaled with the square root of the Josephson critical current density (Jc) universally, as long as the junctions had a low critical current density of less than 1×104 A/cm2 at 4.2 K. These low-Jc junctions exhibited dI/dV profiles peculiar to inelastic tunneling via two or less localized states with some remnant of a smeared superconducting gap. In contrast, we could not observe a universal scaling relation between IcRn and Jc among higher-Jc junctions. The maximum IcRn values of IEJs having Jc ranging from 104 to 106 A/cm2 were limited to 2–3 mV at 4.2 K. The dI/dV profiles of these high-Jc junctions differed considerably from those of low-Jc junctions, and were characterized by a highly smeared-out superconducting gap with a reproducible sub-gap structure. The differential conductance at high bias voltages increased slightly with decreasing temperature. These results indicate that a simple tunneling picture is inadequate to describe IEJs with high-Jc values.


Physica C-superconductivity and Its Applications | 2003

HTS-SFQ ring oscillator circuit fabricated with a novel multilayer structure

Hiroshi Katsuno; Toshihiko Nagano; Kohei Nakayama; Jiro Yoshida

Abstract A novel multilayer structure composed of a NBCO groundplane and stannate isolation layers was fabricated in order to improve the quality of Josephson characteristics and wiring layers on a buried groundplane. The fabricated junctions exhibited high magnetic modulation of I c exceeding 90% and an I c R n product of 0.75 mV at 30 K. The sheet inductances of the counter-electrode and the base-electrode wiring were 1.1 and 1.3 pH, respectively, nearly independent of a temperature ranging from 20 to 30 K. We also fabricated an HTS-SFQ ring oscillator circuit including 21 junctions by adopting this novel multilayer and confirmed a proper operation of the ring oscillator at 20–30 K. The maximum output voltage of the ring oscillator was observed to be 0.06 mV at 30 K and 0.12 mV at 20 K, indicating the signal delay time per stage to be 3.4 and 1.8 ps, respectively.


IEEE Transactions on Applied Superconductivity | 2003

Interface-engineered junctions with YbBaCuO as the counter-electrode

Jiro Yoshida; Hiroshi Katsuno; Kohei Nakayama; Shinji Inoue; Toshihiko Nagano

The electric properties of interface-engineered junctions with YbBa/sub 2/Cu/sub 3/O/sub 7/ as the counter-electrode were investigated. The junctions exhibited excellent Josephson characteristics with the critical current density (J/sub c/) ranging from 10/sup 2/ A/cm/sup 2/ to more than 10/sup 6/ A/cm/sup 2/, and the normal resistance (R/sub n/) ranging from 10/sup -6/ /spl Omega/cm/sup 2/ to 10/sup -9/ /spl Omega/cm/sup 2/. The R/sub n/ values varied approximately in accordance with J/sub c//sup -p/, where p was close to 0.25 for low-J/sub c/ junctions and increased gradually up to 0.75 for high-J/sub c/ junctions. The junctions with R/sub n/ exceeding 10/sup -7/ /spl Omega/cm/sup 2/ exhibited dI/dV profiles peculiar to tunneling processes via localized states. The dI/dV profiles of the junctions with lower R/sub n/ were characterized by reproducible fine structures below 15 mV, probably due to multiple Andreev reflections. These results indicate that the crossover from the tunneling regime to metallic weak-links takes place in these junctions depending on the process conditions.


Archive | 2007

Semiconductor light emitting device and semiconductor light emitting apparatus

Hiroshi Katsuno; Yasuo Ohba; Kei Kaneko; Mitsuhiro Kushibe


Archive | 2009

Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus

Hiroshi Katsuno; Yasuo Ohba; Kei Kaneko; Mitsuhiro Kushibe


Archive | 2011

Semiconductor light emitting device and wafer

Kei Kaneko; Yasuo Ohba; Hiroshi Katsuno; Mitsuhiro Kushibe


Archive | 2010

Semiconductor light emitting device, wafer, method for manufacturing semiconductor light emitting device, and method for manufacturing wafer

Mitsuhiro Kushibe; Yasuo Ohba; Hiroshi Katsuno; Kei Kaneko; Shinji Yamada


Archive | 2009

Semiconductor element, semiconductor device, semiconductor wafer, and method of growing semiconductor crystal

Katsura Kaneko; Hiroshi Katsuno; Mitsuhiro Kushibe; Yasuo Oba; 弘 勝野; 康夫 大場; 光弘 櫛部; 桂 金子

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