Toshihiko Tanaka

A new method of harmonic power detection based on the instantaneous active power in three-phase circuits

This paper presents a new method of harmonic power detection based on the instantaneous active power in three-phase circuits, and its applications to search for dominant harmonic sources in power systems. The proposed method requires only band elimination filters and a three-phase active power meter to detect the harmonic active power, and it is able to deal with harmonic power flow more easily and precisely than a conventional meter which is based on Fourier series of single-phase circuits. In addition, measurement errors of the harmonic power are discussed theoretically. The validity of the proposed method is demonstrated by digital simulation. >

Reducing supply current harmonics

In this article, a simple and effective method for reducing the supply current harmonics has been proposed for a parallel connected 12-pulse thyristor converter with an interphase reactor. The proposed method requires only an interphase reactor with an optimal inductance value being much smaller than conventional inductance values, without any additional devices or components. The supply current waveform of the 12-pulse thyristor converter with the optimal interphase reactor is more sinusoidal than that of a 36-pulse thyristor converter. The proposed design concept of the interphase reactor has been discussed, and confirmed by using digital computer simulation. An experimental system has been constructed and tested, and the experimental results have verified the practicability and effectiveness. The authors conclude that the proposed concept provides a clean power utility interface for various industrial/utility applications including superconducting energy storage systems (SMES).

A new buck-boost-operation-based sinusoidal inverter circuit

This paper proposes a novel sinusoidal inverter circuit. The performance of this inverter circuit is based on buck-boost operation, as it is well known in a DC chopper circuit. The proposed inverter has a distinguished feature of step-up and step-down output voltage. The sinusoidal output voltage of the inverter is obtained by using a hysteresis-comparator scheme. The behavior of the inverter circuit is described in detail based on the switching conditions and operation modes. The computer simulation is carried out in order to confirm the performance and advantage of the proposed sinusoidal inverter.

A novel method of reducing the supply current harmonics of a 12-pulse thyristor rectifier with an interphase reactor

A novel design concept of an interphase reactor in a three-phase twelve-pulse thyristor rectifier is proposed for reducing supply current harmonics. This concept requires only an interphase reactor with a small inductance value, and requires no additional switching devices. As the inductance value is decreased, the supply current approaches a sinusoidal waveform, which is more sinusoidal than that of a 36-pulse thyristor rectifier. The basic principle of the proposed concept is discussed in detail, and confirmed by using digital computer simulation. Experimental results verify the effectiveness and practicability of the proposed design concept of the interphase reactor.

Development of actinic full-field EUV mask blank inspection tool at MIRAI-Selete

We have developed an actinic full-field EUV mask blank inspection tool that consists of an EUV light source, a 26X Schwarzschild optics for dark-field imaging, an EUV-sensitive backside-illuminated charge-coupled-device (BI-CCD) camera, and a mechanical mask stage with a stroke range of 160 mm. A critical illumination system is employed by setting ellipsoidal and plane mirrors to illuminate an area of mask blank that is to be inspected. Since in this setup a circular area on the mask blank with approximately 0.8 mm diameter is illuminated, a 0.5×0.5 mm2 square image area can be addressed without moving the mask stage. The inspection tool can also be operated under time delay and integration (TDI) mode by scanning the mask stage with a constant velocity. In spite of comparatively large effective pixel size of 500 nm on the mask blank, small defect-to-pixel ratio such as 0.12 for phase defect of 60 nm in width and 1.5 nm in height, was established as a measured value of defect detection sensitivity by using both static imaging mode and time-delay and integration (TDI) operation mode.

A method of compensating harmonic currents generated by consumer electronic equipment using the correlation function

This paper proposes a novel method of compensating harmonic currents generated by consumer electronic equipment that act as harmonic voltage sources, using the correlation function. The distribution transformer is equipped with an additional winding on the secondary side, and a single-phase voltage-source pulse-width-modulated (PWM) inverter is connected to the added winding, acting as a shunt-active filter. The leakage inductor of the added winding behaves as though connected in series to the leakage inductor on the secondary side winding connected to the consumer electronic equipment. The shunt-active filter can thus be used to compensate harmonic currents on the source side without an inductor series-connected to the harmonic voltage source. The basic principle of the proposed compensation method is discussed in detail. Digital computer simulation is implemented to demonstrate the validity and practicability of the proposed compensation method using the proposed harmonic current detection method using the correlation function.

Actinic phase defect detection and printability analysis for patterned EUVL mask

Multilayer defects embedded in EUV mask blanks are of primary concern in making usable mask because the multilayer defects as small as 1.5 nm in height cause phase shifts and are most likely to be printable on wafers. To detect such phase defects, we have developed an actinic (at wavelength) full-field EUV mask blank inspection tool equipped with dark-field imaging optics. Inspection performance was demonstrated by a full-field mask blank inspection of a test mask blank to detect its programmed phase defects and native phase defects. A potential of detecting phase defects among the absorber patterns was also explored by inspecting masks with dot bump defects sitting among the absorber lines and line bump defects perpendicular to the absorber lines. For the phase defect printability study, the test mask was exposed using an EUV exposure tool (EUV1) at Selete. Simulation of projected image was also conducted using FDTD method. Multilayer defect printability for varying location of the multilayer phase defects relative to the absorber line patterns were evaluated

Actinic Mask Blank Inspection and Signal Analysis for Detecting Phase Defects Down to 1.5 nm in Height

The capability of an actinic (at-wavelength) inspection system for extreme ultraviolet lithography (EUVL) mask blank has been analyzed by experiment and simulation. The actinic inspection optics, that we developed to obtain a two-dimensional dark field image, consists of illumination optics, Schwarzschild optics with concave and convex mirrors as dark-field imaging optics, and a back-illuminated charge-coupled-device (BI-CCD). A test mask blank with programmed bump defects of smaller sizes and lower heights compared to those used in a previous work was fabricated and the bump defects were detected by the tool. The inspection experiments demonstrated that fabricated multilayer defects down to 1.5 nm in top height and 60 nm in width can be successfully detected. The simulation further indicated that the inspection optics performed well in detecting phase defects of 1.5 nm in height and 40 nm in width.

Flare evaluation for 32-nm half pitch using SFET

Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be 6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD, we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This research was supported in part by NEDO.

A new approach to the capacitor-commutated converter for HVDC-a combined commutation-capacitor of active and passive capacitors

This paper introduces a new approach to the capacitor-commutated converter (CCC) for HVDC. A small-rated three-phase voltage-source PWM converter is connected between a series commutation capacitor and thyristor rectifier through matching transformers. The PWM converter acts as auxiliary commutation-capacitor for the thyristor rectifier while the series capacitor acts as the main commutation capacitor. The capacitance, which is the sum of the small-rated active and series passive capacitors, is variable, so that stable commutation is obtained. In CCCs commutation failure occurs when the AC bus voltage is recovered whereas the proposed combined commutation-capacitor can achieve successful commutation for both rapidly decreasing and increasing AC bus voltages. The basic principle of the proposed active-passive capacitor commutated converter is discussed in detail. Then, constant margin-angle control with a constant firing angle of the thyristor converter is proposed using a function generator block. Digital simulation demonstrates the novelty and effectiveness of the proposed active-passive capacitor commutated converter.