Yukiyasu Arisawa

Flare evaluation for 32-nm half pitch using SFET

Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be 6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD, we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This research was supported in part by NEDO.

Light-shield border impact on the printability of extreme-ultraviolet mask

When a thinner absorber mask is applied to extreme ultraviolet (EUV) lithography for chip production, it becomes essential to a introduce light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. In this paper, we evaluate the leakage of both EUV and out-of-band from light-shield border and clarify the dependence of lithographic performance on light-shield border structure using a small field exposure tool with/without spectral purify filter (SPF). Then we evaluate the lithographic performance of a thin absorber EUV mask with light-shield border of the etched multilayer type and demonstrate the merit of its structure using a full-field scanner operating under the currently employed condition of EUV source in which SPF is not installed.

EUV flare correction for the half-pitch 22nm node

Extreme ultraviolet lithography (EUVL) is one of the most promising candidates for the next-generation lithography. For the adoption of EUVL, however, there are some technological issues to be solved. One of the critical issues is flare which is an undesirable scattered light that reduces the aerial image contrast leading to a reduction in the process window such as exposure latitude. Therefore, new methods to compensate for the anticipated flare effect have to be devised. At Selete, flare correction based on a flare point-spread function (PSF) is investigated. We succeeded in achieving a CD control of within a few nm over various pattern densities for the half-pitch (HP) 32-nm node. However, our estimation shows that the previous flare correction scheme could not meet the accuracy criteria of flare computation for HP 22-nm node. Therefore, we have modified the flare correction flow to implement a variable gridding for pattern-density calculation. The variable gridding based on the shape of a PSF enables highly accurate flare calculation within a reasonable runtime. Furthermore, we will use model-based OPC for HP 22-nm node, whereas we normally use rule-based OPC for HP 32- nm node. This is because the lithography process is reaching the low k1 regime. In this work, we investigate the feasibility of model-based OPC incorporating flare correction.

Simulation Analysis of the Characteristics of a High Magnification Imaging Optics for the Observation of Extreme Ultraviolet Lithography Mask to Predict Phase Defect Printability

By employing simulation, we analyzed the characteristic of the optics of high-magnification multilayer-coated mirror employed for the examination of extreme ultraviolet lithography (EUVL) mask, and we also examined the performance of phase defect printability prediction. The imaging optics comprises Schwarzschild optics and a concave mirror; and it is modeled as an imaging means with an annular-shaped pupil. In this simulation, tilted coherent illumination that was successfully applied in an EUV microscope constructed at a beamline of the NewSUBARU, was assumed. Observation images of mask patterns affected by phase defects were simulated assuming EUVL masks representing half pitches of 16 and 11 nm generations; and those simulated results were compared with the simulated reduction-projection images on wafer formed by an exposure tool. Although the high-magnification observation optics does not completely emulate the printed pattern images on wafer it predicts the existence of phase defects and predict the value of their impacts.

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Thin absorber EUV mask with light-shield border of etched multilayer and its lithographic performance

When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.

Impact of EUV mask roughness on lithography performance

The influence of surface roughness of an EUV mask on wafer image has been thoroughly investigated by lithography simulation with the Monte Carlo method. Based on the power spectral density of the surface roughness of an actual mask, and based on a given random phase distribution, we have reconstructed a number of rough surfaces with various rms roughness values. We quantitatively estimated the impacts of these reconstructed rough surfaces on wafer images. Furthermore, we also investigated the influence of phase defects formed on the rough surfaces. We then did the process margin analysis that showed the specifications of the surface roughness.

Phase defect printability analyses: dependence of defect type and EUV exposure condition

Phase defect printability and imaging characteristics were investigated by using aerial image simulation to clarify the phase defect impact on patterns depending on defect types, and on exposure conditions. In particular, the difference between the impacts caused by the same size bump phase defect and pit phase defect on 28 nm ~ 16 nm L&S projected patterns were investigated by calculating line width variations. Aerial images of phase defects in an absence of any absorber pattern were also calculated, and the image intensity losses of the two types of defects were compared. For a dipole illumination with 0.25 NA (numerical aperture) the pit phase defect impact was found to be stronger than the bump phase defect impact, when the two defect widths were less than 70% of the half-pitch of L&S patterns on the mask. This occurrence was not foreseen by the defect image calculation. On the other hand, for circular illumination with 0.33 NA, the bump defect impact was found to be stronger than the pit phase defect impact, which was consistent with the defect image calculation results. The contribution of dipole illumination in lowering the phase defect impact was confirmed for both bump and pit phase defects.

Flare Impact and Correction for Critical Dimension Control with Full-Field Exposure Tool

Extreme ultraviolet lithography (EUVL) requires flare variation compensation technology and highly accurate critical dimension (CD) control for the fabrication of devices with feature sizes of 32 nm and beyond. To deal with these issues, a mask pattern suitable for evaluating flare and CD variation was designed based on the power spectral density (PSD) of the projection optics of the EUV1. The CD of the replicated patterns clearly varied with the local density of mask patterns, and the variation was affected by mask CD error and flare level. The impact of flare on CD variation was estimated very precisely (<±2 nm) from aerial simulations that took into account the flare level based on the PSD and resist blur, which was modeled as a simple Gaussian function. Mask resizing was found to be useful in compensating for flare variations and was used in the fabrication of the metal-layer patterns for a 22-nm-node static random access memory.

Impact of the phase defect structure on an actinic dark-field blank inspection signal and wafer printability

A variety of phase defects (PDs) such as programmed bump and pit PDs, and native bump and pit PDs were detected by a dark-field ABI (Actinic Blank Inspection) tool. Among the PDs, some of them seemed to grow and propagate in an angular direction, away from substrate surface as was found by a TEM analysis. This presentation reports on the influence of 3-D phase defect on wafer printability, and on defect detection signals of an ABI tool. The result shows that the impact of the inclination angle on printing performance was quite significant when the PDs were not covered with the absorber pattern. On the other hand, the defect detection signal intensity was negligibly small in the case where the inclination angle was less than 9 degrees. However, ABI with its high magnification optics can pinpoint the PDs actual location as defined by the EUV light, rather than the ones that are not so clearly define by the surface topography.