Toshimi Kawahara

SuperCSP/sup TM/

SuperCSP is fabricated by building up the interposer with high reliability encapsulant on the chip by wafer level packaging technology. New encapsulation technology enables real chip-sized package from a package perspective. It is also a known good encapsulated die (KGED) from a die perspective. The reasons why board level reliability of SuperCSP is good regardless of extremely low bump-standoff height are as follows. (1) The C.T.E of encapsulant for SuperCSP is close to that of motherboard, so that the encapsulant layer effectively reduces stress occurring in the solder interconnecting portion. (2) Encapsulant with high adhesive strength reinforces and fixes the delicate connecting portion of chip and post, and also does not allow its deformation. (3) Connecting portion of solder ball and post has a strong structure and can tolerate the stress because solder balls catch hold of the whole surface of metal posts, which stick out from the encapsulant and have a mound like structure.

Development of CSP using Au ball bumps as external connection terminals

We developed a new-structure, fine-pitch chip size package (CSP) with Au ball bumps used as external connection terminals. In the manufacturing process, a substrate consisting of a base material made of a Cu alloy (0.3Cr-0.25Sn-0.2Zn-Cu) and spot Ag plating applied to one side was used as a temporary interposer. After the molding process, only the substrate was dissolved selectively, and an interposer-less structure was realized. We founded that we can directly connect Au ball bumps to tip balls of Au wires exposed on the back surface of a package by applying etching dissolution to a substrate. Thus, terminals can now be arranged in as fine a pitch as a wire bonding pitch. We verified that each bond between a Au ball bump and a Au wire has sufficient strength, and the strength did not decrease after 1000 cycles of -55/spl deg/C/+125/spl deg/C. We attempted mounting on board using the Au-Au bonding method with an insulating adhesive. No void occurred in the connection areas, and the electrodes on the substrate were properly deformed and connected. After 1400 cycles of -55/spl deg/C/+125/spl deg/C, electric resistance of interconnect portion did not decrease, and thus, a high degree of mounting reliability was confirmed.

Fine Pitch CSP Technology Using Au Ball Bumps as External Terminals

l.Introduction In the development of CSPs, the bump pitches have already been reduced to 0.5mm or 0.4mm. In the first half of year 2000, the pitch is estimated to reduce to 0.3mm. The CSP development currently in vogue is an area anay type CSP typified by fine pitch BGA(Ball Grid Array). This type of CSP can cover a wide range of numbers of I/Os. Unlike peripheral placement packages such as the existing 0.3mm pitch QFP(Quad Flat Package), however, it is necessary to draw out the wires to draw out the wires on the substrate immediately under the package after mounting the chip. Therefore, as the bump pitch reduces, it may be necessary to use a multilayer substrate, resulting in the increase in cost and limiting the application of the package. In addition, soldering is widely used as a bump material in the present CSP but elimination of lead is an issue we cannot qvoid even if soldering is continued to be used as a material for the bump of the fine pitch CSP. Before CSPs are put into practice use and widely used, we will have many technical hurdles to get over. Therefore, Au ball bumps, which has been used for bare chip assemblies, were applied as external terminals and a trial CSP was produced where these bumps were arranged just inside edges of the CSP. This paper reports the new structure and assembly technology of this CSP.