Toshinari Takayanagi

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC

Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.