Toshinori Maeda

A mixed-signal 0.18-/spl mu/m CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD RAM and ROM systems. It integrates a 32-b RISC CPU, formatter, servo digital signal processor (DSP), 16-Mb DRAM, error correction code (ECC), ATA interface, and partial-response-maximum-likelihood (PRML) read channel with 7-b interpolated parallel analog-to-digital converter (ADC). Increasing the bus bandwidth by using embedded DRAM, a hardware ECC engine, and four parallel digital finite-impulse response (FIR) filters contributes to the high playback speed of 16/spl times/. PR(3,4,4,3) architecture has been used in the read channel system for optical disc systems. The obtained wide tangential tilt margin of /spl plusmn/0.6/spl deg/ is due to the use of this PRML read channel technique. The interpolated parallel scheme has attained a high number of effective bits of 6.3 for 72-Mz input frequency at 432-MSample/s operation without any calibration technique, with low power consumption of 180 mW in a small core size of 1.05 mm/sup 2/. This SoC has been fabricated in 0.18-/spl mu/m 1PS3AL CMOS embedded DRAM technology. It contains 24 million transistors in a 144-mm/sup 2/ die and consumes 1.2 W at 432-MSample/s operation. This low power consumption allows the use of a low-cost plastic package. As a result, we can compose highly reliable DVD RAM and ROM systems with this SoC and some tiny components.

A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store

A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using a data-flow clocking scheme. A floating-point unit performs single- and double-precision floating-point operations concurrently with an integer unit. The chip is fabricated using 0.8- mu m double-metal CMOS technology. About 1M transistors are contained in the 14.85*15. 13-mm die housed in a 238-pin pin-grid array (PGA).<<ETX>>

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >