Toshinori Sueyoshi

Hierarchical routing bus

In MIMD highly parallel processing systems, such as parallel computers and data flow computers, their capability, cost, and implementability are dependent largely on the implementation of their access mechanis m. This paper proposes a hierarchical routing bus (H-R bus) which is useful as an access mechanism for such system s. In the H-R bus, 3-port bus switches, called T switches, are connected in a hierarchical fashio n. This bus has the following characteristics; (1) a modular structure, thus yielding high expandability, and when many modules are added, its access multiplicity increases; (2) when a system becomes large, its average access distance does not increase greatly; (3) in case of an access contention and collision, distributed arbitration is possible without a deadlock; (4) it requires a small amount of hardware, and a simple interfac e. It is known that any hierarchy-structured multiprocessor system contains a bottleneck, which causes a problem for highly parallel processin g. This paper considers this issue and shows that the bottleneck effect is not so large in memory-shared multiprocessor systems of fast access tim e. Finally, a method of removing the bottleneck of the H-R bus by using 4-port bus switches (called TT switches) is presented.

INSIGHT: an interconnection network simulator for massively parallel computers

Presents an interconnection network simulator, called INSIGHT, to evaluate the performance of various interconnection networks toward the realization of massively parallel computers. The capability of INSIGHT to modify the simulation parameters support the development of large-scale interconnection networks. In this study, we consider the requirements of a simulator to evaluate the performance of large-scale interconnection networks, and describe the framework of INSIGHT. Moreover, we examined the effects on the communication performance or execution time in relation to the performance of the processors. As a result, in e-cube routing, we found out that in some cases, the wormhole flow control method, which achieved low communication latency, has low performance compared to the store-and-forward method.<<ETX>>

The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures

The reconfigurable parallel processor system under development at Kyushu University is an MIMD-type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N × N crossbar networks (currently S is 1). Each PE (Processing Element) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set, an MMU (Memory Management Unit) with 64K bytes of cache, 4M bytes of memory, and an MCU (Message Communication Unit). The modular 128 × 128 crossbar network is implemented by arranging 256 identical 8 × 8 crossbar LSI-modules in a 16 × 16 matrix form. The full 128-PE configuration achieves supercomputer levels of performance by providing 1.28 GIPS and 205 MFLOPS of computing power, 512M bytes of memory, and 2.56G bytes/s of inter-PE communication bandwidth. At the same time, it exploits unique reconfigurability in the memory and intercommunication architectures. By utilizing these two types of reconfigurability, we believe that the system can be effectively tailored to a wide spectrum of applications such as numerical computation, image processing, computer graphics, artificial intelligence, neurocomputing, and so on.

Recursive diagonal torus (RDT): An interconnection network for the massively parallel computers

This paper proposes the recursive diagonal torus (RDT), which is the interconnection network for the massively parallel computer with 2 16 or more processors. RDT can realize a small diameter (12 for 16 Knode) with a small number of links compared to the hypercube by adding links recursively along the diagonal direction of the two-dimensional torus. The packet is routed by a simple algorithm called vector routing. RDT not only includes a torus, but also easily implements the emulation of the hypercube or tree as well as the packet broadcast. Considering a typical packet transfer method, the random transfer performance is evaluated. A satisfactory result is obtained compared to the 2-D or 3-D torus, although somewhat inferior to the hypercube with a large number of links.