Toshio Sakakibara

High Channel Mobility of MOSFET Fabricated on 4H-SiC (11-20) Face Using Wet Annealing

We studied the annealing process to improve the field-effect channel mobility (μFE) on the 4H-SiC (11-20) face. We found that wet annealing, in which a wet atmosphere was maintained during the cooling-down period to 600°C after wet oxidation, was effective. The interface states (Dit) near the conduction band edge decreased and the μFE increased up to 244 cm2/Vs. Furthermore, the origin of this high channel mobility was investigated using secondary ion mass spectroscopy (SIMS) measurement and thermal desorption spectroscopy (TDS) analysis. It was indicated that the hydrogen density at the MOS interface was increased by the wet annealing and the hydrogen was desorbed mainly at temperatures between 800 °C and 900 °C. These hydrogen desorption temperatures also corresponded to the temperatures of the μFE reduction by argon annealing after the wet annealing. These results indicated that this high channel mobility was achieved by hydrogen passivation during the wet annealing at temperatures between 800 °C and 900 °C.

1200-V JBS Diodes with Low Threshold Voltage and Low Leakage Current

4H-SiC SBDs have been developed by many researchers and commercialized for power application devices in recent years. At present time, the issues of an SiC-SBD are lower on-state current and a relatively larger-leakage current at the reverse bias than Si-PN diodes. A JBS (Junction Barrier Schottky) diode was proposed as a structure to realize a lower leakage current. We simulated the electrical characteristics of JBS diodes, where the Schottky electrode was made of molybdenum in order to optimize its performance. We fabricated JBS diodes based on the simulation with a diameter of 3.9mm (11.9 mm2). The JBS diode has a lower threshold voltage of 0.45 V, a large forward current of 40 A at Vf = 2.5V and a high breakdown voltage of 1660 V. Furthermore, the leakage current at 1200 V was remarkably low (Ir = 20 nA).

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

(11-20) Face Channel MOSFET with Low On-Resistance

We have investigated the techniques to improve the channel mobility of SiC MOSFETs and found that the hydrogen termination of dangling bonds at a MOS interface is very effective in improving the channel mobility, particularly that of the interface fabricated on a (11-20) face wafer. A high channel mobility of MOSFET on the (11-20) face was achieved to 244cm2/Vs by new process which can terminate dangling bonds by hydrogen. The vertical MOSFET, which is prepared using this process, has a low on-resistance of 5.7 mΩcm2 and a breakdown voltage of 1100 V. The channel resistance is estimated at 0.58 mΩcm2.

600 V 100 A 4H-SiC Junction Barrier Schottky Diode with Guard Rings Termination

4H-SiC SBDs have been commercialized for power application devices. However, the maximum current of these SBDs is 20A. In this work, we designed a JBS (junction barrier Schottky) diode structure and the fabrication processes to be optimized. The current and breakdown voltage were over 100 A and 660 V at Ir = 1 mA/cm2, respectively. The recovery characteristics of the JBS diode are much superior to those of the Si-FRD while it is comparable to those of the commercially available SiC-SBD at elevated temperatures up to 125°C..

First Principles Theoretical Study of 4H-SiC/SiO2 Interfacial Electronic States on (0001), (0001), and (1120)

Interfacial electronic states of 4H-SiC/SiO2 on (0001), (0001), and (1120) are studied by means of ab initio calculations. We find that the calculated densities of localized inversion traps are in the increasing order from (1120), (0001), to (0001).

Ab Initio Calculations of SiO2/SiC Interfaces and High Channel Mobility MOSFET with (11-20) Face

Ab initio calculations were carried out to study the origin of the trap at the SiO2/SiC (MOS: Metal-Oxide-Semiconductor) interface with the three different faces of the substrate, (0001), (000-1), and (11-20). In a previous report we experimentally discovered that the (11-20) face is suitable for high channel mobility. The calculation in this report showed that the MOS interface achieved the intermediate states due to distortion and thus acted like an interface trap. The interface trap density of the MOS interface on the (11-20) face substrate was smaller than those on the other faces. The interface trap densities were 2.14, 3.36, and 1.40 in units of 1015 cm-2 for the above listed substrate orientations, respectively. For clarity, the channel mobility was compared experimentally to reveal that it realized a larger value for the (11-20) substrate than the other two faces. From our results, we concluded that (11-20) face substrate was more suitable for high power device applications than the (0001) face or (000-1) face substrates.

Effect of Hydrogenation on the Dangling-Bond Free 4H-SiC(1120)/SiO2 Interface Studied by Ab Initio Calculations

Ab initio calculation method is used to study the effect of hydrogenation at two different stages of the 4H-SiC(1120)/SiO2 interface, which is initially constructed to have no dangling bond states. We find that the electronic density of states near the conduction band edge in this structure decreases by dissolving the Si–C bonds connecting the SiC and SiO2 structures via hydrogenation.