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Dive into the research topics where Jun Sakakibara is active.

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Featured researches published by Jun Sakakibara.


international symposium on power semiconductor devices and ic's | 2008

600V-class Super Junction MOSFET with High Aspect Ratio P/N Columns Structure

Jun Sakakibara; Yoshitaka Noda; Takumi Shibata; Shoji Nogami; Tomonori Yamaoka; Hitoshi Yamaguchi

A Super Junction (SJ) MOSFET with high aspect ratio p/n columns structure has been proposed to improve the trade-off relationship between breakdown voltage and specific on-resistance (Ron)- We have proposed a new trench filling epitaxial growth technique to fabricate this structure. In this work, we tried to apply this method to 600 V-class SJ-MOSFETs. We succeeded in fabricating p/n columns structure of which the aspect ratio is 25. It shows that its Ron is lower than that of IGBTs, and is the lowest in the reported 600 V-class Si devices.


international symposium on power semiconductor devices and ic's | 2013

A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics

Hidefumi Takaya; Jun Morimoto; Kimimori Hamada; Toshimasa Yamamoto; Jun Sakakibara; Yukihiko Watanabe; Narumasa Soejima

A 4H-SiC trench MOSFET has been developed that features the use of trench gates with a thick oxide layer on the bottoms of the trenches for relieving the electric field strength of the gate oxide layer. The maximum electric field strength and gate-drain charge (Qgd) of this device is 46% and 38% lower than that of a conventional MOSFET, respectively. A □5mm chip was fabricated with a thick oxide layer under the trench. The drain-source breakdown voltage (BVdss) of this chip is 1400V and the specific on-resistance (Ron.sp) is 4.4mΩcm2 (Vg=20V, Vd=2V). A high breakdown voltage is obtained by a wide trench terminal structure and trench separation.


international symposium on power semiconductor devices and ic's | 2006

Breakthrough of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage

Hitoshi Yamaguchi; Jun Sakakibara; Yasushi Urakami

Under 100V breakdown voltage, a new device structure is required for the purpose of reducing on-resistance and for high reliability. In this study, it was demonstrated that the Si limit of on-resistance was broken by Super 3D MOSFET structure in an actual prototype fabrication. This Super 3D MOSFET has a wide current path in the depth direction without enlarging its surface area. Its on-resistance was 16.4 m¿·mm2 at the breakdown voltage of 58V. This on-resistance was below the Si limit and the lowest result ever reported. Moreover, it was clarified that the UIS (unclamped inductive switching) endurance of this device was 3.08 J/cm2 with 3 mm × 3 mm size chip and this result was 1.5 times stronger than that of conventional structure. This Super 3D structure was fabricated by simplified trench filling epitaxial process and high aspect ratio trench etching process. The Super 3D MOSFET is very attractive for automotive motor drive use.


international symposium on power semiconductor devices and ic s | 2003

Ultra low on-resistance Super 3D MOSFET

Hitoshi Yamaguchi; Naohiro Suzuki; Jun Sakakibara

For the purpose of reducing the power MOSFET on-resistance in the range of under 300V breakdown voltage, we have already proposed a new power MOSFET hat we call the Super 3D MOSFET. At 70V breakdown voltage, the simulated total specific on-resistance was 19 m/spl Omega/-mm/sup 2/ and below the R/sub on/ Si limit. In this work, we present the structural design for source and drain resistance in order to utilize the widened channel and drift path effectively. And also we mention the manufacturing influence of the in-depth distribution such as gate oxide thickness and doping concentration of drift layer to reduce the specific on-resistance. Furthermore, we will present the experimental results concerning the on-resistance reduction by deepening the structure.


Materials Science Forum | 2013

4H-SiC Trench MOSFET with Thick Bottom Oxide

Hidefumi Takaya; Jun Morimoto; Toshimasa Yamamoto; Jun Sakakibara; Yukihiko Watanabe; Narumasa Soejima; Kimimori Hamada

A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.


Archive | 1998

Method for manufacturing a semiconductor substrate

Masaki Matsui; Shoichi Yamauchi; Hisayoshi Ohshima; Kunihiro Onoda; Akiyoshi Asai; Takanari Sasaya; Takeshi Enya; Jun Sakakibara


Archive | 2003

Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench

Shoichi Yamauchi; Hitoshi Yamaguchi; Jun Sakakibara; Nobuhiro Tsuji


Archive | 1997

Semiconductor integrated circuit device and manufacturing method for the same

Akiyoshi Asai; Jun Sakakibara; Megumi Suzuki; Seiji Fujino


Archive | 2000

Semiconductor device having trench filled up with gate electrode

Hitoshi Yamaguchi; Toshio Sakakibara; Jun Sakakibara; Takumi Shibata; Toshiyuki Morishita


Archive | 2003

Method of manufacturing semiconductor device having trench filled up with gate electrode

Hitoshi Yamaguchi; Toshio Sakakibara; Jun Sakakibara; Takumi Shibata; Toshiyuki Morishita

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