Toshio Shimoe

A development of a high speed ATM switching LSIC

An IC designed for a high-speed broadband ISDN (integrated services digital network) switching system is described. The IC was fabricated using a Bi-CMOS RAM and logic gate array. The IC has functions for cell buffering, switching, and VCI conversion. It features a pipeline configuration and a high-speed ECL (emitter coupled logic) interface for a throughput of 1.2 Gbit/s. Tests confirmed accurate switching and high-speed operation up to 110 MHz, which corresponds to 1.8 Gbit/s throughput. An ATM (asynchronous transfer mode) switching system handling 512 150 Mbit/s channels can be constructed using this IC, and housed in four cabinets.<<ETX>>

Experimental broadband ATM switching system

The authors describe an ATM (asynchronous transfer mode) switching architecture based on a self-routing principle and an experimental system constructed by connecting self-routing modules in a three-stage link configuration. The architecture is called multistage self-routing (MSSR). It is confirmed that MSSR switching can deal with various media such as voice, data, and video.<<ETX>>

Rectangularly configured 4*4 Ti:LiNbO/sub 3/ matrix switch with low drive voltage

A matrix switch with a novel architecture has been demonstrated. A rectangularly configured 4*4 switch has been designed and fabricated on a 65-mm-long z-cut Ti:LiNbO/sub 3/ chip. The average drive voltage of 16 Delta beta -reversal directional couplers is 9 V for a cross state and 20 V for a bar state. The drive voltage difference of 11 V is about half that of the conventional matrix switch. Drive voltage deviations are within +or-0.5 V. The average insertion loss is 4.7 dB, and deviations for different paths are within +or-0.3 dB, and deviations for different paths are within +or-0.3 dB. The crosstalk of all crosspoint switches is also estimated based on crosstalk output measurements. >

Photonic ATM.Switching Network

This paper proposes a photonic ATM switching network using multi-input optical buffer memory based on wavelength division switching.