Toshio Yamamura

A 120mm 2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology

High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.