Kazuhisa Kanazawa

A 56-nm CMOS 99-

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the worlds first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size

{\hbox {mm}}^{2}

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.

8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.

A 70nm 16Gb 16-level-cell NAND Flash Memory

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

Today NAND Flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. Figure 13.6.1 shows the memory-density trend since 2003. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2b/cell MLC technology was introduced. Recently, MLC NAND flash memories with more than 2b/cell [1,2] have been reported.

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-/spl mu/s random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-/spl mu/m single-metal CMOS process resulting in a die size of 120 mm/sup 2/ and an effective cell size of 1.1 /spl mu/m/sup 2/.

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Fabricated in 56nm CMOS technology, an 8Gb multi-level NAND Flash memory occupies 98.8mm2, with a memory cell size of 0.0075mum/b. The 10MB/s programming and 93ms block copy are also realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks

A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed

Rapidly increasing solid-state mass-storage application areas are requiring low cost, high density flash memories with higher read and program throughputs. This paper describes a 3.3 V-only 64 Mb NAND flash memory fabricated using a 0.4 /spl mu/m single-metal CMOS technology. The read throughput of 40 MB/s is achieved by improving the random access time and by introducing a full-chip burst read. A typical program throughput of 5 MB/s corresponding to 180 ns/byte is achieved by using a narrow incremental step pulse programming (NISPP) technique. A staggered row decoder scheme relaxes layout limitations and improves the random access time.

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.

A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed

A 36-ns, 1-Mb EPROM using a unique pseudodifferential sensing technique for high speed and a new noise immunity technique has been developed. In order to achieve both high speed and small die size, a newly developed pseudodifferential sensing technique with single-ended bit lines (one transistor/cell) and only two reference bit lines has been implemented, instead of a conventional fully differential sensing technique which has the disadvantage of large die size. A new data transfer circuit whose data transfer speed is controlled by an address transition detection pulse is utilized to obtain high noise immunity against power line noise caused by charging or discharging an output capacitance. Using 0.9-μm lithography, a cell size of 3.1 μm×2.9 μm has been achieved, resulting in a small die size of 6.67 mm×6.56 mm. The chip is fabricated by an n-well CMOS double poly-Si process with polycide technology and a single metal