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Featured researches published by Toshitaka Fukushima.


Microelectronics Reliability | 1985

Field programmable device with circuitry for detecting poor insulation between adjacent word lines

Kouji Ueno; Toshitaka Fukushima; Kazumi Koyama

A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.


Japanese Journal of Applied Physics | 1980

Beam Loading Effect on Capture Efficiency in Radio Frequency Acceleration in Electron Synchrotron

Takeshi Katayama; Toshitaka Fukushima; Tatsuya Yamakawa

The effects of beam-loading on the RF field in the cavity and on the beam capture to the electron synchrotron from the injector linac have been studied experimentally and theoretically. In the present experiment, the amplitude and the phase of the RF field, which is a superposition of the external driving field and the beam-induced field, have been found to change during the transient period just after the injection from the linac. This phenomenon is striking, especially when the frequency of the external driving field is very different from the resonant frequency of the cavity. In this detuning of the cavity, a large capture efficiency of the injected beam from the linac has been observed. The mechanism of this has been elucidated by analyzing the effects of the beam-induced field in the cavity during the transient period.


international solid-state circuits conference | 1983

A 40ns junction-shorting PROM

Toshitaka Fukushima; K. Ueno; Y. Matsuzaki; K. Tanaka

An 8K×8b junction-shorting PROM using a selective power-switching circuit in dual stage decoders will be detailed. Shallow V-groove isolation and wafer stepper process technologies resulted in a 7.14mm × 5.28mm chip with a 168μ2cell size.


IEEE Transactions on Electron Devices | 1983

An advanced SVG technology for 64K junction-shorting PROM's

Toshitaka Fukushima; Kouji Ueno; K. Tanaka

The memory cell size of the 64 kbit PROM was reduced to 168µm2(0.26 mil2) by using advanced SVG (Shallow V-Groove) isolation and the wafer stepper process. SVG isolation was introduced in 1979 to suppress the SCR latching between two neighboring cells in the 4 kbit junction-shorting PROM. Since then, the cell size has been reduced until it became limited by the widths of word and bit lines. In the 64 kbit PROM, the SVG isolation technology was improved to achieve self-alignment in diffusion, to provide a high breakdown voltage for Schottky diodes, and to increase the flexibility of the mask layout. The size of the peripheral circuitry was thus reduced to allow a smaller cell size and a smaller parasitic capacitance. The memory cell array occupies 45.0 percent of the total die size of 7.14 × 5.28 mm2.


Japanese Journal of Applied Physics | 1991

Measurement of Beam Bunch Length in the 1.3-GeV Electron Synchrotron

Masayuki Mutou; Koichi Maruyama; Toshitaka Fukushima; Yoshikazu Miyahara; Katsuhide Yoshida

We observed the bunch structure of the circulating beam in the 1.3-GeV Electron Synchrotron (ES) for the first time. The ES operated at a repetition rate of 21 Hz and an rf frequency of 138 MHz. The bunch length variation during the rf acceleration was determined by measuring time distributions of photons produced by the synchrotron radiation. The observed lengths show a rapid decrease from 1.83 to 0.72 ns (FWHM) in the 2-5 ms time interval after the start of acceleration (energy range 0.1-0.25 GeV), and they are almost constant, 0.6-0.7 ns, by the end of acceleration (0.25-1.1 GeV). The behavior is well reproduced by a calculation taking into account the effects of the adiabatic damping, radiation damping, and radiation excitation.


Archive | 1989

Semiconductor programmable memory device

Toshitaka Fukushima


Archive | 1988

Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon

Toshitaka Fukushima


Archive | 1988

Method of forming groove isolation filled with dielectric for semiconductor device

Toshitaka Fukushima


Archive | 1979

Three-state output circuit

Toshitaka Fukushima; Kouji Ueno


Archive | 1980

Programmable read-only memory device

Toshitaka Fukushima; Kazumi Koyama; Kouji Ueno

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